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phy/efinix: Directly exclude IOs when primitive is used, avoid having to do it in user design.

This commit is contained in:
Florent Kermarrec 2023-08-30 08:54:46 +02:00
parent f0c876ca77
commit b201aeb083
2 changed files with 28 additions and 19 deletions
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5
liteeth/phy/titaniumrgmii.py
View File

@ -52,6 +52,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
"drive_strength" : 4 # FIXME: Get it from constraints.
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.tx_data)
# TX Ctl IOs.
# -----------
@ -76,6 +77,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
"drive_strength" : 4 # FIXME: Get it from constraints.
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.tx_ctl)
# Logic.
# ------
@ -123,6 +125,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
"is_inclk_inverted" : False
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.rx_data)
# RX Ctl IOs.
# -----------
@ -168,6 +171,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "INPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.rx)
self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk)
cmd = "create_clock -period {} auto_eth_rx_clk".format(1e9/125e6)
@ -184,6 +188,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "OUTPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.tx)
# TX PLL.
# -------

4
liteeth/phy/trionrgmii.py
View File

@ -52,6 +52,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
"drive_strength" : 4 # FIXME: Get it from constraints.
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.tx_data)
# TX Ctl IOs.
# -----------
@ -99,6 +100,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
"is_inclk_inverted" : False
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.rx_data)
# RX Ctl IOs.
# -----------
@ -144,6 +146,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "INPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.rx)
self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk)
cmd = "create_clock -period {} auto_eth_rx_clk".format(1e9/125e6)
@ -160,6 +163,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "OUTPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.tx)
# TX PLL.
# -------