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phy/efinix: Directly exclude IOs when primitive is used, avoid having to do it in user design.

This commit is contained in:
Florent Kermarrec 2023-08-30 08:54:46 +02:00
parent f0c876ca77
commit b201aeb083
2 changed files with 28 additions and 19 deletions
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5
liteeth/phy/titaniumrgmii.py
View File

@ -52,6 +52,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
"drive_strength" : 4 # FIXME: Get it from constraints.
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.tx_data)
# TX Ctl IOs.
# -----------
@ -76,6 +77,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
"drive_strength" : 4 # FIXME: Get it from constraints.
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.tx_ctl)
# Logic.
# ------
@ -123,6 +125,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
"is_inclk_inverted" : False
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.rx_data)
# RX Ctl IOs.
# -----------
@ -168,6 +171,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "INPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.rx)
self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk)
cmd = "create_clock -period {} auto_eth_rx_clk".format(1e9/125e6)
@ -184,6 +188,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "OUTPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.tx)
# TX PLL.
# -------

42
liteeth/phy/trionrgmii.py
View File

@ -31,27 +31,28 @@ class LiteEthPHYRGMIITX(LiteXModule):
tx_data_h = []
tx_data_l = []
for n in range(4):
name = platform.get_pin_name(pads.tx_data[n])
pad = platform.get_pin_location(pads.tx_data[n])
io_prop = platform.get_pin_properties(pads.tx_data[n])
name = f"auto_{name}"
name = platform.get_pin_name(pads.tx_data[n])
pad = platform.get_pin_location(pads.tx_data[n])
io_prop = platform.get_pin_properties(pads.tx_data[n])
name = f"auto_{name}"
tx_data_h.append(platform.add_iface_io(name + "_HI"))
tx_data_l.append(platform.add_iface_io(name + "_LO"))
tx_data_h.append(platform.add_iface_io(name + "_HI"))
tx_data_l.append(platform.add_iface_io(name + "_LO"))
block = {
"type" : "GPIO",
"mode" : "OUTPUT",
"name" : name,
"location" : pad,
"properties" : io_prop,
"size" : 1,
"out_reg" : "DDIO_RESYNC",
"out_clk_pin" : "auto_eth_tx_clk",
"is_inclk_inverted" : False,
"drive_strength" : 4 # FIXME: Get it from constraints.
}
platform.toolchain.ifacewriter.blocks.append(block)
block = {
"type" : "GPIO",
"mode" : "OUTPUT",
"name" : name,
"location" : pad,
"properties" : io_prop,
"size" : 1,
"out_reg" : "DDIO_RESYNC",
"out_clk_pin" : "auto_eth_tx_clk",
"is_inclk_inverted" : False,
"drive_strength" : 4 # FIXME: Get it from constraints.
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.tx_data)
# TX Ctl IOs.
# -----------
@ -99,6 +100,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
"is_inclk_inverted" : False
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(pads.rx_data)
# RX Ctl IOs.
# -----------
@ -144,6 +146,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "INPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.rx)
self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk)
cmd = "create_clock -period {} auto_eth_rx_clk".format(1e9/125e6)
@ -160,6 +163,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
"mode" : "OUTPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.tx)
# TX PLL.
# -------