From b2e12724ccdfc9e620e553b066fe33a7c4abe9cc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 1 Mar 2020 19:09:55 +0100 Subject: [PATCH] phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints). --- liteeth/phy/a7_1000basex.py | 4 +++- liteeth/phy/ecp5rgmii.py | 4 +++- liteeth/phy/gmii.py | 4 +++- liteeth/phy/gmii_mii.py | 4 +++- liteeth/phy/k7_1000basex.py | 4 +++- liteeth/phy/ku_1000basex.py | 4 +++- liteeth/phy/mii.py | 4 +++- liteeth/phy/rmii.py | 4 +++- liteeth/phy/s6rgmii.py | 4 +++- liteeth/phy/s7rgmii.py | 4 +++- liteeth/phy/usrgmii.py | 4 +++- 11 files changed, 33 insertions(+), 11 deletions(-) diff --git a/liteeth/phy/a7_1000basex.py b/liteeth/phy/a7_1000basex.py index 54a2381..dca2c80 100644 --- a/liteeth/phy/a7_1000basex.py +++ b/liteeth/phy/a7_1000basex.py @@ -41,7 +41,9 @@ class Gearbox(Module): class A7_1000BASEX(Module): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, qpll_channel, data_pads, sys_clk_freq): pcs = PCS(lsb_first=True) self.submodules += pcs diff --git a/liteeth/phy/ecp5rgmii.py b/liteeth/phy/ecp5rgmii.py index fda78cd..349f14b 100644 --- a/liteeth/phy/ecp5rgmii.py +++ b/liteeth/phy/ecp5rgmii.py @@ -176,7 +176,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index 57326ed..ec42698 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -83,7 +83,9 @@ class LiteEthPHYGMIICRG(Module, AutoCSR): class LiteEthPHYGMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, clock_pads, pads, with_hw_init_reset=True): self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads)) diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index 7c61363..1d8c516 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -170,7 +170,9 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR): class LiteEthPHYGMIIMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True): # Note: we can use GMII CRG since it also handles tx clock pad used for MII self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq) diff --git a/liteeth/phy/k7_1000basex.py b/liteeth/phy/k7_1000basex.py index 565b55c..49f8a15 100644 --- a/liteeth/phy/k7_1000basex.py +++ b/liteeth/phy/k7_1000basex.py @@ -42,7 +42,9 @@ class Gearbox(Module): # Configured for 200MHz transceiver reference clock class K7_1000BASEX(Module): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq): pcs = PCS(lsb_first=True) self.submodules += pcs diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py index 5d399c1..c500c8f 100644 --- a/liteeth/phy/ku_1000basex.py +++ b/liteeth/phy/ku_1000basex.py @@ -41,7 +41,9 @@ class Gearbox(Module): # Configured for 200MHz transceiver reference clock class KU_1000BASEX(Module): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq): pcs = PCS(lsb_first=True) self.submodules += pcs diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index 110bfce..5734cd6 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -90,7 +90,9 @@ class LiteEthPHYMIICRG(Module, AutoCSR): class LiteEthPHYMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 25e6 + rx_clk_freq = 25e6 def __init__(self, clock_pads, pads, with_hw_init_reset=True): self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads)) diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 61aee95..ddcad62 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -118,7 +118,9 @@ class LiteEthPHYRMIICRG(Module, AutoCSR): class LiteEthPHYRMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 50e6 + rx_clk_freq = 50e6 def __init__(self, clock_pads, pads, with_hw_init_reset=True): self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, with_hw_init_reset) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads)) diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 6a0684c..5f4c70a 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -258,7 +258,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index 9cc4bd2..7394bb5 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -202,7 +202,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py index 099ea72..32bdc4e 100644 --- a/liteeth/phy/usrgmii.py +++ b/liteeth/phy/usrgmii.py @@ -212,7 +212,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): - dw = 8 + dw = 8 + tx_clk_freq = 125e6 + rx_clk_freq = 125e6 def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))