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test/mac_wishbone_tb: fix simulation

This commit is contained in:
Florent Kermarrec 2016-03-25 12:26:02 +01:00
parent b7f3b3ef42
commit b394f2f45e
1 changed files with 8 additions and 6 deletions
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14
test/mac_wishbone_tb.py
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@ -60,9 +60,11 @@ class SRAMReaderDriver:
yield
def clear_done(self):
yield self.obj.ev.done.clear.eq(1)
yield self.obj.ev.pending.re.eq(1)
yield self.obj.ev.pending.r.eq(1)
yield
yield self.obj.ev.done.clear.eq(0)
yield self.obj.ev.pending.re.eq(0)
yield self.obj.ev.pending.r.eq(0)
yield
@ -75,9 +77,11 @@ class SRAMWriterDriver:
yield
def clear_available(self):
yield self.obj.ev.available.clear.eq(1)
yield self.obj.ev.pending.re.eq(1)
yield self.obj.ev.pending.r.eq(1)
yield
yield self.obj.ev.available.clear.eq(0)
yield self.obj.ev.pending.re.eq(0)
yield self.obj.ev.pending.r.eq(0)
yield
@ -103,8 +107,6 @@ def main_generator(dut):
errors = 0
for i in range(2):
for i in range(20):
yield
for slot in range(2):
print("slot {}: ".format(slot), end="")
# fill tx memory