From b4c3223a241b434992abf11681a143163e5f6c14 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 27 Sep 2015 19:14:46 +0200 Subject: [PATCH] update litescope and build Devel targets in test --- example_designs/targets/base.py | 10 ++++----- example_designs/targets/etherbone.py | 10 ++++----- example_designs/targets/tty.py | 10 ++++----- example_designs/targets/udp.py | 10 ++++----- example_designs/test/test_la.py | 23 --------------------- example_designs/test/test_logic_analyzer.py | 23 +++++++++++++++++++++ test/Makefile | 12 +++++++---- 7 files changed, 51 insertions(+), 47 deletions(-) delete mode 100644 example_designs/test/test_la.py create mode 100644 example_designs/test/test_logic_analyzer.py diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index 92eb6cd..84d2097 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -59,11 +59,11 @@ set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] class BaseSoCDevel(BaseSoC): csr_map = { - "la": 20 + "logic_analyzer": 20 } csr_map.update(BaseSoC.csr_map) def __init__(self, platform): - from litescope.frontend.la import LiteScopeLA + from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer from litescope.core.port import LiteScopeTerm BaseSoC.__init__(self, platform) @@ -127,8 +127,8 @@ class BaseSoCDevel(BaseSoC): self.core_udp_rx_fsm_state, self.core_udp_tx_fsm_state ) - self.submodules.la = LiteScopeLA(debug, 4096) - self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) + self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) + self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) def do_finalize(self): BaseSoC.do_finalize(self) @@ -148,6 +148,6 @@ class BaseSoCDevel(BaseSoC): ] def do_exit(self, vns): - self.la.export(vns, "test/la.csv") + self.logic_analyzer.export(vns, "test/logic_analyzer.csv") default_subtarget = BaseSoC diff --git a/example_designs/targets/etherbone.py b/example_designs/targets/etherbone.py index c94c275..b3dec12 100644 --- a/example_designs/targets/etherbone.py +++ b/example_designs/targets/etherbone.py @@ -16,11 +16,11 @@ class EtherboneSoC(BaseSoC): class EtherboneSoCDevel(EtherboneSoC): csr_map = { - "la": 20 + "logic_analyzer": 20 } csr_map.update(EtherboneSoC.csr_map) def __init__(self, platform): - from litescope.frontend.la import LiteScopeLA + from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer from litescope.core.port import LiteScopeTerm EtherboneSoC.__init__(self, platform) debug = ( @@ -61,10 +61,10 @@ class EtherboneSoCDevel(EtherboneSoC): self.etherbone.master.bus.bte, self.etherbone.master.bus.err ) - self.submodules.la = LiteScopeLA(debug, 4096) - self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) + self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) + self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) def do_exit(self, vns): - self.la.export(vns, "test/la.csv") + self.logic_analyzer.export(vns, "test/logic_analyzer.csv") default_subtarget = EtherboneSoC diff --git a/example_designs/targets/tty.py b/example_designs/targets/tty.py index 3f3cfc8..00d1202 100644 --- a/example_designs/targets/tty.py +++ b/example_designs/targets/tty.py @@ -16,11 +16,11 @@ class TTYSoC(BaseSoC): class TTYSoCDevel(TTYSoC): csr_map = { - "la": 20 + "logic_analyzer": 20 } csr_map.update(TTYSoC.csr_map) def __init__(self, platform): - from litescope.frontend.la import LiteScopeLA + from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer from litescope.core.port import LiteScopeTerm TTYSoC.__init__(self, platform) debug = ( @@ -32,10 +32,10 @@ class TTYSoCDevel(TTYSoC): self.tty.source.ack, self.tty.source.data ) - self.submodules.la = LiteScopeLA(debug, 4096) - self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) + self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) + self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) def do_exit(self, vns): - self.la.export(vns, "test/la.csv") + self.logic_analyzer.export(vns, "test/logic_analyzer.csv") default_subtarget = TTYSoC diff --git a/example_designs/targets/udp.py b/example_designs/targets/udp.py index f24d446..ab62acd 100644 --- a/example_designs/targets/udp.py +++ b/example_designs/targets/udp.py @@ -27,11 +27,11 @@ class UDPSoC(BaseSoC): class UDPSoCDevel(UDPSoC): csr_map = { - "la": 20 + "logic_analyzer": 20 } csr_map.update(UDPSoC.csr_map) def __init__(self, platform): - from litescope.frontend.la import LiteScopeLA + from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer from litescope.core.port import LiteScopeTerm UDPSoC.__init__(self, platform) debug = ( @@ -59,10 +59,10 @@ class UDPSoCDevel(UDPSoC): self.loopback_32.source.ack, self.loopback_32.source.data ) - self.submodules.la = LiteScopeLA(debug, 4096) - self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) + self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) + self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) def do_exit(self, vns): - self.la.export(vns, "test/la.csv") + self.logic_analyzer.export(vns, "test/logic_analyzer.csv") default_subtarget = UDPSoC diff --git a/example_designs/test/test_la.py b/example_designs/test/test_la.py deleted file mode 100644 index c011382..0000000 --- a/example_designs/test/test_la.py +++ /dev/null @@ -1,23 +0,0 @@ -import time -from litescope.software.driver.la import LiteScopeLADriver - - -def main(wb): - la = LiteScopeLADriver(wb.regs, "la", debug=True) - - wb.open() - regs = wb.regs - # # # - conditions = {} - la.configure_term(port=0, cond=conditions) - la.configure_sum("term") - # Run Logic Analyzer - la.run(offset=2048, length=4000) - - while not la.done(): - pass - - la.upload() - la.save("dump.vcd") - # # # - wb.close() diff --git a/example_designs/test/test_logic_analyzer.py b/example_designs/test/test_logic_analyzer.py new file mode 100644 index 0000000..b25138a --- /dev/null +++ b/example_designs/test/test_logic_analyzer.py @@ -0,0 +1,23 @@ +import time +from litescope.software.driver.logic_analyzer import LiteScopeLogicAnalyzerDriver + + +def main(wb): + logic_analyzer = LiteScopeLADriver(wb.regs, "logic_analyzer", debug=True) + + wb.open() + regs = wb.regs + # # # + conditions = {} + logic_analyzer.configure_term(port=0, cond=conditions) + logic_analyzer.configure_sum("term") + # Run Logic Analyzer + logic_analyzer.run(offset=2048, length=4000) + + while not logic_analyzer.done(): + pass + + logic_analyzer.upload() + logic_analyzer.save("dump.vcd") + # # # + wb.close() diff --git a/test/Makefile b/test/Makefile index 4a7e964..4b461cd 100644 --- a/test/Makefile +++ b/test/Makefile @@ -33,9 +33,13 @@ etherbone_tb: $(CMD) etherbone_tb.py example_designs: - cd ../example_designs && $(PYTHON) make.py -t base -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t udp -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t etherbone -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t tty -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t base -s BaseSoC -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t base -s BaseSoCDevel -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t udp -s UDPSoC -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t udp -s UDPSoCDevel -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t etherbone -s EtherboneSoC -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t etherbone -s EtherboneSoCDevel -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t tty -s TTYSoC -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t tty -s TTYSoCDevel -p kc705 -Ob run False build-bitstream all: model_tb mac_core_tb arp_tb ip_tb udp_tb icmp_tb etherbone_tb example_designs \ No newline at end of file