From b573e1267cecdd0fe0e12afdbc2f8d3e1e990fd7 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 16 Sep 2024 11:35:33 +0200
Subject: [PATCH] phy/xgmii: Add Clk/Data Pads definition to avoid duplication
 in PHYs.

---
 liteeth/phy/xgmii.py | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/liteeth/phy/xgmii.py b/liteeth/phy/xgmii.py
index 4efc3c4..bad44f6 100644
--- a/liteeth/phy/xgmii.py
+++ b/liteeth/phy/xgmii.py
@@ -17,6 +17,18 @@ XGMII_IDLE  = Constant(0x07, bits_sign=8)
 XGMII_START = Constant(0xFB, bits_sign=8)
 XGMII_END   = Constant(0xFD, bits_sign=8)
 
+# Pads/Interfaces ----------------------------------------------------------------------------------
+
+class LiteEthPHYXGMIIClkPads:
+    rx = Signal()
+    tx = Signal()
+
+class LiteEthPHYXGMIIPads:
+    rx_ctl  = Signal(8)
+    rx_data = Signal(64)
+    tx_ctl  = Signal(8)
+    tx_data = Signal(64)
+
 # LiteEth PHY XGMII TX -----------------------------------------------------------------------------
 
 class LiteEthPHYXGMIITX(LiteXModule):
@@ -649,7 +661,7 @@ class LiteEthPHYXGMIICRG(LiteXModule):
         else:
             self.comb += [
                 self.cd_eth_rx.clk.eq(clock_pads.rx),
-                self.cd_eth_tx.clk.eq(clock_pads.tx)
+                self.cd_eth_tx.clk.eq(clock_pads.tx),
             ]
 
 # LiteEth PHY XGMII --------------------------------------------------------------------------------