From b7443f5fd32a3315bc6a434e297a18a94e75e323 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 4 Apr 2024 13:36:16 +0200 Subject: [PATCH] gen/mac: Allow 16-bit data_width. --- liteeth/gen.py | 2 +- liteeth/mac/crc.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 6acd0ef..21dd72f 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -559,7 +559,7 @@ class UDPCore(PHYCore): ip_address = ip_address, clk_freq = core_config["clk_freq"], dw = data_width, - with_sys_datapath = (data_width == 32), + with_sys_datapath = data_width in [16, 32], tx_cdc_depth = tx_cdc_depth, tx_cdc_buffered = tx_cdc_buffered, rx_cdc_depth = rx_cdc_depth, diff --git a/liteeth/mac/crc.py b/liteeth/mac/crc.py index 994046c..4e2d610 100644 --- a/liteeth/mac/crc.py +++ b/liteeth/mac/crc.py @@ -155,7 +155,7 @@ class LiteEthMACCRC32Inserter(LiteXModule): # Parameters. data_width = len(sink.data) ratio = 32//data_width - assert data_width in [8, 32, 64] + assert data_width in [8, 16, 32, 64] # Signals. crc_packet = Signal(32) @@ -275,7 +275,7 @@ class LiteEthMACCRC32Checker(LiteXModule): # Parameters. data_width = len(sink.data) ratio = ceil(32/data_width) - assert data_width in [8, 32, 64] + assert data_width in [8, 16, 32, 64] # CRC32 Checker. self.crc = crc = LiteEthMACCRC32(data_width)