Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen/mac: Allow 16-bit data_width.

This commit is contained in:
Florent Kermarrec 2024-04-04 13:36:16 +02:00
parent c18cfb8bc0
commit b7443f5fd3
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
liteeth/gen.py
View File

@ -559,7 +559,7 @@ class UDPCore(PHYCore):
ip_address = ip_address,
clk_freq = core_config["clk_freq"],
dw = data_width,
with_sys_datapath = (data_width == 32),
with_sys_datapath = data_width in [16, 32],
tx_cdc_depth = tx_cdc_depth,
tx_cdc_buffered = tx_cdc_buffered,
rx_cdc_depth = rx_cdc_depth,

4
liteeth/mac/crc.py
View File

@ -155,7 +155,7 @@ class LiteEthMACCRC32Inserter(LiteXModule):
# Parameters.
data_width = len(sink.data)
ratio = 32//data_width
assert data_width in [8, 32, 64]
assert data_width in [8, 16, 32, 64]
# Signals.
crc_packet = Signal(32)
@ -275,7 +275,7 @@ class LiteEthMACCRC32Checker(LiteXModule):
# Parameters.
data_width = len(sink.data)
ratio = ceil(32/data_width)
assert data_width in [8, 32, 64]
assert data_width in [8, 16, 32, 64]
# CRC32 Checker.
self.crc = crc = LiteEthMACCRC32(data_width)