core/arp: Switch LiteEthARPCache to a proper Memory and allow multiple entries.
This commit is contained in:
Florent Kermarrec
parent
dc7ed0de6f
commit
b74618d1ed
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@ -15,7 +15,7 @@ from liteeth.core.icmp import LiteEthICMP
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# IP Core ------------------------------------------------------------------------------------------
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class LiteEthIPCore(Module, AutoCSR):
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def __init__(self, phy, mac_address, ip_address, clk_freq, dw=8,
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def __init__(self, phy, mac_address, ip_address, clk_freq, arp_entries=1, dw=8,
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with_icmp = True,
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with_ip_broadcast = True,
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with_sys_datapath = False,
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@ -49,6 +49,7 @@ class LiteEthIPCore(Module, AutoCSR):
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mac_address = mac_address,
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ip_address = ip_address,
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clk_freq = clk_freq,
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entries = arp_entries,
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dw = dw,
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)
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@ -74,7 +75,7 @@ class LiteEthIPCore(Module, AutoCSR):
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# UDP IP Core --------------------------------------------------------------------------------------
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class LiteEthUDPIPCore(LiteEthIPCore):
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def __init__(self, phy, mac_address, ip_address, clk_freq, dw=8,
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def __init__(self, phy, mac_address, ip_address, clk_freq, arp_entries=1, dw=8,
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with_icmp = True,
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with_ip_broadcast = True,
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with_sys_datapath = False,
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@ -94,6 +95,7 @@ class LiteEthUDPIPCore(LiteEthIPCore):
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mac_address = mac_address,
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ip_address = ip_address,
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clk_freq = clk_freq,
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arp_entries = arp_entries,
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with_icmp = with_icmp,
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dw = dw,
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with_ip_broadcast = with_ip_broadcast,
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@ -156,9 +156,8 @@ class LiteEthARPRX(LiteXModule):
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# ARP Cache ----------------------------------------------------------------------------------------
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class LiteEthARPCache(LiteXModule):
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class LiteEthARPCache(Module):
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def __init__(self, entries, clk_freq):
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assert entries == 1
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# Update interface.
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self.update = stream.Endpoint([("ip_address", 32), ("mac_address", 48)])
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@ -168,37 +167,83 @@ class LiteEthARPCache(LiteXModule):
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# # #
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# Note: Store only 1 IP/MAC couple, can be improved with a real
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# table in the future to improve performance when packets are
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# targeting multiple destinations.
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cached_valid = Signal()
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cached_ip_address = Signal(32, reset_less=True)
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cached_mac_address = Signal(48, reset_less=True)
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self.cached_timer = WaitTimer(int(clk_freq*10))
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entries = max(entries, 2)
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self.comb += self.update.ready.eq(1)
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self.sync += [
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If(self.update.valid,
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cached_valid.eq(1),
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cached_ip_address.eq(self.update.ip_address),
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cached_mac_address.eq(self.update.mac_address),
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).Else(
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If(self.cached_timer.done,
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cached_valid.eq(0)
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)
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mem_width = 32 + 48 + 1 # IP + MAC + Valid.
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mem = Memory(mem_width, entries)
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mem_wr_port = mem.get_port(write_capable=True)
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mem_rd_port = mem.get_port(async_read=True) # FIXME: Avoid async_read.
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self.specials += mem, mem_wr_port, mem_rd_port
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update_count = Signal(max=entries)
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search_count = Signal(max=entries)
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error = Signal()
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mem_wr_port_valid = mem_wr_port.dat_w[80]
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mem_wr_port_ip_address = mem_wr_port.dat_w[0:32]
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mem_wr_port_mac_address = mem_wr_port.dat_w[32:80]
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mem_rd_port_valid = mem_rd_port.dat_r[80]
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mem_rd_port_ip_address = mem_rd_port.dat_r[0:32]
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mem_rd_port_mac_address = mem_rd_port.dat_r[32:80]
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self.submodules.fsm = fsm = FSM(reset_state="CLEAR")
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fsm.act("CLEAR",
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mem_wr_port.we.eq(1),
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mem_wr_port.adr.eq(update_count),
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mem_wr_port_valid.eq(0),
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NextValue(update_count, update_count + 1),
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If(update_count == (entries - 1),
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NextState("IDLE")
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)
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]
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self.comb += self.cached_timer.wait.eq(~self.update.valid)
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self.comb += self.request.ready.eq(1)
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self.comb += self.response.valid.eq(self.request.valid)
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self.comb += self.response.error.eq(~cached_valid | (self.request.ip_address != cached_ip_address))
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self.comb += self.response.mac_address.eq(cached_mac_address)
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)
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fsm.act("IDLE",
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If(self.update.valid,
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NextState("MEM_UPDATE")
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),
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If(self.request.valid,
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NextValue(search_count, 0),
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NextState("MEM_SEARCH")
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)
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)
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fsm.act("MEM_UPDATE",
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mem_wr_port.we.eq(1),
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mem_wr_port.adr.eq(update_count),
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mem_wr_port_valid.eq(1),
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mem_wr_port_ip_address.eq( self.update.ip_address),
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mem_wr_port_mac_address.eq(self.update.mac_address),
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self.update.ready.eq(1),
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If(update_count == (entries - 1),
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NextValue(update_count, 0)
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).Else(
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NextValue(update_count, update_count + 1)
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),
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NextState("IDLE")
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)
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fsm.act("MEM_SEARCH",
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mem_rd_port.adr.eq(search_count),
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If(mem_rd_port_valid & (mem_rd_port_ip_address == self.request.ip_address),
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NextValue(error, 0),
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NextState("RESPONSE")
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).Elif(search_count == (entries - 1),
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NextValue(error, 1),
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NextState("RESPONSE")
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).Else(
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NextValue(search_count, search_count + 1)
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)
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)
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fsm.act("RESPONSE",
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self.request.ready.eq(1),
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self.response.valid.eq(1),
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self.response.error.eq(error),
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self.response.mac_address.eq(mem_rd_port_mac_address),
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NextState("IDLE")
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)
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# ARP Table ----------------------------------------------------------------------------------------
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class LiteEthARPTable(LiteXModule):
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def __init__(self, clk_freq, max_requests=8):
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def __init__(self, clk_freq, entries=1, max_requests=8):
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self.sink = sink = stream.Endpoint(_arp_table_layout) # from arp_rx
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self.source = source = stream.Endpoint(_arp_table_layout) # to arp_tx
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@ -215,7 +260,7 @@ class LiteEthARPTable(LiteXModule):
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self.request_timer = WaitTimer(100e-3*clk_freq)
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self.comb += self.request_timer.wait.eq(request_pending & ~self.request_timer.done)
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self.cache = cache = LiteEthARPCache(entries=1, clk_freq=clk_freq)
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self.cache = cache = LiteEthARPCache(entries=entries, clk_freq=clk_freq)
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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@ -274,6 +319,7 @@ class LiteEthARPTable(LiteXModule):
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NextValue(request_ip_address, request.ip_address),
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NextState("SEND_REQUEST")
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).Else(
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NextValue(response.mac_address, cache.response.mac_address),
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NextState("PRESENT_RESPONSE"),
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)
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)
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@ -289,7 +335,6 @@ class LiteEthARPTable(LiteXModule):
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)
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fsm.act("PRESENT_RESPONSE",
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response.valid.eq(1),
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response.mac_address.eq(cache.response.mac_address),
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If(response.ready,
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NextValue(response.failed, 0),
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NextState("IDLE")
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@ -299,10 +344,10 @@ class LiteEthARPTable(LiteXModule):
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# ARP ----------------------------------------------------------------------------------------------
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class LiteEthARP(LiteXModule):
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def __init__(self, mac, mac_address, ip_address, clk_freq, dw=8):
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def __init__(self, mac, mac_address, ip_address, clk_freq, entries=1, dw=8):
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self.tx = tx = LiteEthARPTX(mac_address, ip_address, dw)
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self.rx = rx = LiteEthARPRX(mac_address, ip_address, dw)
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self.table = table = LiteEthARPTable(clk_freq)
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self.table = table = LiteEthARPTable(clk_freq, entries=entries)
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self.comb += [
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rx.source.connect(table.sink),
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table.source.connect(tx.sink)
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