From b7efe0fd46a8b0f5c188eff89e0c2ac0f6975af0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 Mar 2016 15:33:13 +0100 Subject: [PATCH] phy: remove pads_register parameter (does not save enough, priority to simplicity) --- liteeth/phy/gmii.py | 8 ++------ liteeth/phy/gmii_mii.py | 4 ++-- liteeth/phy/mii.py | 8 ++------ liteeth/phy/s6rgmii.py | 2 +- liteeth/phy/s7rgmii.py | 2 +- 5 files changed, 8 insertions(+), 16 deletions(-) diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index 908c331..7801538 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -7,21 +7,17 @@ from liteeth.phy.common import * class LiteEthPHYGMIITX(Module): - def __init__(self, pads, pads_register=True): + def __init__(self, pads): self.sink = sink = Sink(eth_phy_description(8)) # # # if hasattr(pads, "tx_er"): self.sync += pads.tx_er.eq(0) - pads_eq = [ + self.sync += [ pads.tx_en.eq(sink.stb), pads.tx_data.eq(sink.data) ] - if pads_register: - self.sync += pads_eq - else: - self.comb += pads_eq self.comb += sink.ack.eq(1) diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index 25a5eab..54fb004 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -27,11 +27,11 @@ class LiteEthPHYGMIIMIITX(Module): # # # gmii_tx_pads = Record(tx_pads_layout) - gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False) + gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads) self.submodules += gmii_tx mii_tx_pads = Record(tx_pads_layout) - mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False) + mii_tx = LiteEthPHYMIITX(mii_tx_pads) self.submodules += mii_tx demux = Demultiplexer(eth_phy_description(8), 2) diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index cdbeb1e..df59be5 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -11,7 +11,7 @@ def converter_description(dw): class LiteEthPHYMIITX(Module): - def __init__(self, pads, pads_register=True): + def __init__(self, pads): self.sink = sink = Sink(eth_phy_description(8)) # # # @@ -27,14 +27,10 @@ class LiteEthPHYMIITX(Module): sink.ack.eq(converter.sink.ack), converter.source.ack.eq(1) ] - pads_eq = [ + self.sync += [ pads.tx_en.eq(converter.source.stb), pads.tx_data.eq(converter.source.data) ] - if pads_register: - self.sync += pads_eq - else: - self.comb += pads_eq class LiteEthPHYMIIRX(Module): diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 6e89833..889b412 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -11,7 +11,7 @@ from liteeth.phy.common import * class LiteEthPHYRGMIITX(Module): - def __init__(self, pads, pads_register=True): + def __init__(self, pads): self.sink = sink = Sink(eth_phy_description(8)) # # # diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index b82fbf3..6cd34da 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -11,7 +11,7 @@ from liteeth.phy.common import * class LiteEthPHYRGMIITX(Module): - def __init__(self, pads, pads_register=True): + def __init__(self, pads): self.sink = sink = Sink(eth_phy_description(8)) # # #