From cccc0c720a892b8bb0efadfc2ba188b3246ec85e Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 22 Sep 2021 22:26:07 +1000 Subject: [PATCH 1/4] Add support for GMII_MII PHY to gen.py It was missing. It's useful for Wukong Signed-off-by: Benjamin Herrenschmidt --- liteeth/gen.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/liteeth/gen.py b/liteeth/gen.py index df467f9..ee7c438 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -193,6 +193,12 @@ class PHYCore(SoCMini): ethphy = phy( clock_pads = platform.request("gmii_eth_clocks"), pads = platform.request("gmii_eth")) + elif phy in [liteeth_phys.LiteEthPHYGMIIMII]: + assert self.clk_freq >= 125e6 + ethphy = phy( + clock_pads = platform.request("gmii_eth_clocks"), + pads = platform.request("gmii_eth"), + clk_freq = self.clk_freq) elif phy in [liteeth_phys.LiteEthS7PHYRGMII, liteeth_phys.LiteEthECP5PHYRGMII]: assert self.clk_freq >= 125e6 ethphy = phy( From 9b3837e63628c496a2869b5da2e3b79cc717ce36 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 22 Sep 2021 22:27:07 +1000 Subject: [PATCH 2/4] Allow "device" to be specified in yaml Otherwise we don't get the DDROutput overrides and the standalone core fails to generate when using GMII_MII Signed-off-by: Benjamin Herrenschmidt --- liteeth/gen.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index ee7c438..d150d23 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -318,10 +318,12 @@ def main(): core_config[k] = int(float(core_config[k])) # Generate core -------------------------------------------------------------------------------- + if "device" not in core_config: + core_config["device"] = "" if core_config["vendor"] == "lattice": - platform = LatticePlatform("", io=[], toolchain="diamond") + platform = LatticePlatform(core_config["device"], io=[], toolchain="diamond") elif core_config["vendor"] == "xilinx": - platform = XilinxPlatform("", io=[], toolchain="vivado") + platform = XilinxPlatform(core_config["device"], io=[], toolchain="vivado") else: raise ValueError("Unsupported vendor: {}".format(core_config["vendor"])) platform.add_extension(_io) From f2032a422791a73d9950c6d8faff0b26dfbc956d Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 23 Sep 2021 12:24:58 +1000 Subject: [PATCH 3/4] Remove clock asserts They aren't strictly necessary, especially since the MAC can have a wider data path and thus cope with running slightly slower Signed-off-by: Benjamin Herrenschmidt --- liteeth/gen.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index d150d23..ebfb36a 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -179,28 +179,23 @@ class PHYCore(SoCMini): # PHY -------------------------------------------------------------------------------------- phy = core_config["phy"] if phy in [liteeth_phys.LiteEthPHYMII]: - assert self.clk_freq >= 12.5e6 ethphy = phy( clock_pads = platform.request("mii_eth_clocks"), pads = platform.request("mii_eth")) elif phy in [liteeth_phys.LiteEthPHYRMII]: - assert self.clk_freq >= 12.5e6 ethphy = phy( clock_pads = platform.request("rmii_eth_clocks"), pads = platform.request("rmii_eth")) elif phy in [liteeth_phys.LiteEthPHYGMII]: - assert self.clk_freq >= 125e6 ethphy = phy( clock_pads = platform.request("gmii_eth_clocks"), pads = platform.request("gmii_eth")) elif phy in [liteeth_phys.LiteEthPHYGMIIMII]: - assert self.clk_freq >= 125e6 ethphy = phy( clock_pads = platform.request("gmii_eth_clocks"), pads = platform.request("gmii_eth"), clk_freq = self.clk_freq) elif phy in [liteeth_phys.LiteEthS7PHYRGMII, liteeth_phys.LiteEthECP5PHYRGMII]: - assert self.clk_freq >= 125e6 ethphy = phy( clock_pads = platform.request("rgmii_eth_clocks"), pads = platform.request("rgmii_eth"), From 63ff6f47e79f9b93a5b579623bbb7230ab10c659 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 24 Sep 2021 12:19:10 +1000 Subject: [PATCH 4/4] gen: Add clock constraints Otherwise the generated verilog is missing necessary "keep" attributes Signed-off-by: Benjamin Herrenschmidt --- liteeth/gen.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/liteeth/gen.py b/liteeth/gen.py index ebfb36a..11f5a3b 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -207,6 +207,17 @@ class PHYCore(SoCMini): self.submodules.ethphy = ethphy self.add_csr("ethphy") + # Generate timing constraints to ensure the "keep" attribute is properly set + # on the various clocks. This also adds the constraints to the generated xdc + # that can then be "imported" in the project using the core. + eth_rx_clk = getattr(ethphy, "crg", ethphy).cd_eth_rx.clk + eth_tx_clk = getattr(ethphy, "crg", ethphy).cd_eth_tx.clk + from liteeth.phy.model import LiteEthPHYModel + if not isinstance(ethphy, LiteEthPHYModel): + self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) + self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) + # MAC Core ----------------------------------------------------------------------------------------- class MACCore(PHYCore):