diff --git a/bench/xu8_st1.py b/bench/xu8_st1.py new file mode 100755 index 0000000..3f9ed63 --- /dev/null +++ b/bench/xu8_st1.py @@ -0,0 +1,102 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteEth. +# +# Copyright (c) 2023 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.gen import * + +from litex.build.generic_platform import * +from litex_boards.platforms import enclustra_mercury_xu8_pe3 + +from litex.soc.cores.clock import * +from litex.soc.interconnect.csr import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX + +# IOs ---------------------------------------------------------------------------------------------- + +_sfp_io = [ + # SFP. + ("sfp", 0, + Subsignal("txp", Pins("K6")), + Subsignal("txn", Pins("K5")), + Subsignal("rxp", Pins("J4")), + Subsignal("rxn", Pins("J3")) + ), +] + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(LiteXModule): + def __init__(self, platform, sys_clk_freq): + self.cd_sys = ClockDomain() + self.cd_eth = ClockDomain() + + # # # + + self.pll = pll = USMMCM(speedgrade=-1) + pll.register_clkin(platform.request("clk100"), 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_eth, 200e6, buf=None) + +# Bench SoC ---------------------------------------------------------------------------------------- + +class BenchSoC(SoCCore): + def __init__(self, sys_clk_freq=int(125e6)): + platform = enclustra_mercury_xu8_pe3.Platform() + platform.add_extension(_sfp_io) + + # SoCMini ---------------------------------------------------------------------------------- + SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, + ident = "LiteEth bench on XU8/ST1", + ident_version = True + ) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # Etherbone -------------------------------------------------------------------------------- + self.submodules.ethphy = USP_GTH_1000BASEX(self.crg.cd_eth.clk, + data_pads = self.platform.request("sfp", 0), + sys_clk_freq = self.clk_freq) + self.add_etherbone(phy=self.ethphy, buffer_depth=4) + + # SRAM ------------------------------------------------------------------------------------- + self.add_ram("sram", 0x20000000, 0x1000) + + # Leds ------------------------------------------------------------------------------------- + from litex.soc.cores.led import LedChaser + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq + ) + +# Main --------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteEth Bench on XU8/ST1") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + args = parser.parse_args() + + soc = BenchSoC() + builder = Builder(soc, csr_csv="csr.csv") + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + +if __name__ == "__main__": + main() diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py index 52dc3f2..22fedc0 100644 --- a/liteeth/phy/usp_gth_1000basex.py +++ b/liteeth/phy/usp_gth_1000basex.py @@ -882,9 +882,9 @@ class USP_GTH_1000BASEX(LiteXModule): o_TXSYNCDONE = Open(), o_TXSYNCOUT = Open(), ) - tx_bufg_gt_ce = Signal() + tx_bufg_gt_ce = Signal() tx_bufg_gt_clr = Signal() - rx_bufg_gt_ce = Signal() + rx_bufg_gt_ce = Signal() rx_bufg_gt_clr = Signal() self.specials += [ Instance("GTHE4_CHANNEL", **gth_params), @@ -917,11 +917,11 @@ class USP_GTH_1000BASEX(LiteXModule): reset_counter = Signal(max=pll_reset_cycles+1) self.sync += [ If(~gtpowergood, - pll_reset.eq(1), + pll_reset.eq(1), reset_counter.eq(0) ).Else( If(reset_counter == pll_reset_cycles, - pll_reset.eq(0) + pll_reset.eq(0) ).Else( reset_counter.eq(reset_counter + 1) ) @@ -942,10 +942,17 @@ class USP_GTH_1000BASEX(LiteXModule): pcs.tbi_rx.eq(gearbox.rx_data) ] - self.comb += [ - tx_data.eq(gearbox.tx_data_half), - gearbox.rx_data_half.eq(rx_data), - - gearbox.tx_data.eq(pcs.tbi_tx), - pcs.tbi_rx.eq(gearbox.rx_data) + self.debug = [ + gtpowergood, + pll_reset, + pll_locked, + tx_reset, + tx_data, + tx_reset_done, + rx_reset, + rx_data, + rx_reset_done, + self.sink, + self.source, + self.link_up ]