From 85c3ab2c51fcb67a6c12cf19afe49985a9f8cb16 Mon Sep 17 00:00:00 2001 From: Matthias Breithaupt Date: Sun, 14 Jul 2024 22:36:26 +0200 Subject: [PATCH] Only import liteiclink when required As liteiclink is only used in the phy implementations of a few Xilinx/AMD FPGAs, it does not make sense that it would be required to build liteeth for any FPGA. Signed-off-by: Matthias Breithaupt --- liteeth/phy/k7_1000basex.py | 3 +-- liteeth/phy/ku_1000basex.py | 3 +-- liteeth/phy/usp_gth_1000basex.py | 3 +-- liteeth/phy/usp_gty_1000basex.py | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/liteeth/phy/k7_1000basex.py b/liteeth/phy/k7_1000basex.py index 33956cf..d9e9526 100644 --- a/liteeth/phy/k7_1000basex.py +++ b/liteeth/phy/k7_1000basex.py @@ -12,8 +12,6 @@ from litex.gen import * from litex.soc.cores.clock import S7MMCM -from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTXTXInit, GTXRXInit - from liteeth.common import * from liteeth.phy.pcs_1000basex import * @@ -26,6 +24,7 @@ class K7_1000BASEX(LiteXModule): rx_clk_freq = 125e6 tx_clk_freq = 125e6 def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): + from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTXTXInit, GTXRXInit assert refclk_freq in [200e6] self.pcs = pcs = PCS(lsb_first=True) diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py index 080d16c..138562c 100644 --- a/liteeth/phy/ku_1000basex.py +++ b/liteeth/phy/ku_1000basex.py @@ -11,8 +11,6 @@ from migen.genlib.cdc import PulseSynchronizer from litex.gen import * -from liteiclink.serdes.gth3_ultrascale import GTHChannelPLL - from liteeth.common import * from liteeth.phy.pcs_1000basex import * @@ -25,6 +23,7 @@ class KU_1000BASEX(LiteXModule): rx_clk_freq = 125e6 tx_clk_freq = 125e6 def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): + from liteiclink.serdes.gth3_ultrascale import GTHChannelPLL assert refclk_freq in [200e6, 156.25e6] self.pcs = pcs = PCS(lsb_first=True) diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py index 68160f6..2e31500 100644 --- a/liteeth/phy/usp_gth_1000basex.py +++ b/liteeth/phy/usp_gth_1000basex.py @@ -11,8 +11,6 @@ from migen.genlib.cdc import PulseSynchronizer from litex.gen import * -from liteiclink.serdes.gth4_ultrascale import GTHChannelPLL - from liteeth.common import * from liteeth.phy.pcs_1000basex import * @@ -25,6 +23,7 @@ class USP_GTH_1000BASEX(LiteXModule): rx_clk_freq = 125e6 tx_clk_freq = 125e6 def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): + from liteiclink.serdes.gth4_ultrascale import GTHChannelPLL assert refclk_freq in [200e6, 156.25e6] self.pcs = pcs = PCS(lsb_first=True) diff --git a/liteeth/phy/usp_gty_1000basex.py b/liteeth/phy/usp_gty_1000basex.py index 24e5476..a43068c 100644 --- a/liteeth/phy/usp_gty_1000basex.py +++ b/liteeth/phy/usp_gty_1000basex.py @@ -11,8 +11,6 @@ from migen.genlib.cdc import PulseSynchronizer from litex.gen import * -from liteiclink.serdes.gty_ultrascale import GTYChannelPLL - from liteeth.common import * from liteeth.phy.pcs_1000basex import * @@ -25,6 +23,7 @@ class USP_GTY_1000BASEX(LiteXModule): rx_clk_freq = 125e6 tx_clk_freq = 125e6 def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): + from liteiclink.serdes.gty_ultrascale import GTYChannelPLL assert refclk_freq in [200e6, 156.25e6] self.pcs = pcs = PCS(lsb_first=True)