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Merge pull request #164 from VOGL-electronic/optional_liteiclink 

Only import liteiclink when required
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enjoy-digital 2024-08-19 09:17:01 +02:00 committed by GitHub
parent d4fa6a2f4a 85c3ab2c51
commit c04ac8f698
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GPG Key ID: B5690EEEBB952194
4 changed files with 4 additions and 8 deletions
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3
liteeth/phy/k7_1000basex.py
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@ -12,8 +12,6 @@ from litex.gen import *
from litex.soc.cores.clock import S7MMCM from litex.soc.cores.clock import S7MMCM
from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTXTXInit, GTXRXInit
from liteeth.common import * from liteeth.common import *
from liteeth.phy.pcs_1000basex import * from liteeth.phy.pcs_1000basex import *
@ -26,6 +24,7 @@ class K7_1000BASEX(LiteXModule):
rx_clk_freq = 125e6 rx_clk_freq = 125e6
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTXTXInit, GTXRXInit
assert refclk_freq in [200e6] assert refclk_freq in [200e6]
self.pcs = pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)

3
liteeth/phy/ku_1000basex.py
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@ -11,8 +11,6 @@ from migen.genlib.cdc import PulseSynchronizer
from litex.gen import * from litex.gen import *
from liteiclink.serdes.gth3_ultrascale import GTHChannelPLL
from liteeth.common import * from liteeth.common import *
from liteeth.phy.pcs_1000basex import * from liteeth.phy.pcs_1000basex import *
@ -25,6 +23,7 @@ class KU_1000BASEX(LiteXModule):
rx_clk_freq = 125e6 rx_clk_freq = 125e6
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
from liteiclink.serdes.gth3_ultrascale import GTHChannelPLL
assert refclk_freq in [200e6, 156.25e6] assert refclk_freq in [200e6, 156.25e6]
self.pcs = pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)

3
liteeth/phy/usp_gth_1000basex.py
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@ -11,8 +11,6 @@ from migen.genlib.cdc import PulseSynchronizer
from litex.gen import * from litex.gen import *
from liteiclink.serdes.gth4_ultrascale import GTHChannelPLL
from liteeth.common import * from liteeth.common import *
from liteeth.phy.pcs_1000basex import * from liteeth.phy.pcs_1000basex import *
@ -25,6 +23,7 @@ class USP_GTH_1000BASEX(LiteXModule):
rx_clk_freq = 125e6 rx_clk_freq = 125e6
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
from liteiclink.serdes.gth4_ultrascale import GTHChannelPLL
assert refclk_freq in [200e6, 156.25e6] assert refclk_freq in [200e6, 156.25e6]
self.pcs = pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)

3
liteeth/phy/usp_gty_1000basex.py
View File

@ -11,8 +11,6 @@ from migen.genlib.cdc import PulseSynchronizer
from litex.gen import * from litex.gen import *
from liteiclink.serdes.gty_ultrascale import GTYChannelPLL
from liteeth.common import * from liteeth.common import *
from liteeth.phy.pcs_1000basex import * from liteeth.phy.pcs_1000basex import *
@ -25,6 +23,7 @@ class USP_GTY_1000BASEX(LiteXModule):
rx_clk_freq = 125e6 rx_clk_freq = 125e6
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
from liteiclink.serdes.gty_ultrascale import GTYChannelPLL
assert refclk_freq in [200e6, 156.25e6] assert refclk_freq in [200e6, 156.25e6]
self.pcs = pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)