From c05de191e2e7674c9d5c0f612db97eac87dac17a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 18 Jan 2024 13:27:32 +0100 Subject: [PATCH] liteeth_gen: Add specific A7_1000BASEX support and example configuration. Adapted from known working targets but untested on hardware. --- examples/udp_a7_gtp_sgmii.yml | 26 +++++++++++++++++++++++ liteeth/gen.py | 39 +++++++++++++++++++++++++++-------- 2 files changed, 56 insertions(+), 9 deletions(-) create mode 100644 examples/udp_a7_gtp_sgmii.yml diff --git a/examples/udp_a7_gtp_sgmii.yml b/examples/udp_a7_gtp_sgmii.yml new file mode 100644 index 0000000..6e04423 --- /dev/null +++ b/examples/udp_a7_gtp_sgmii.yml @@ -0,0 +1,26 @@ +# +# This file is part of LiteEth. +# +# Copyright (c) 2020-2024 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +# PHY ---------------------------------------------------------------------- +phy : A7_1000BASEX +vendor : xilinx +toolchain : vivado + +# Core --------------------------------------------------------------------- +refclk_freq : 200e6 +clk_freq : 25e6 +core : udp +data_width : 32 +dhcp : True + +# UDP Ports -------------------------------------------------------------------- +udp_ports: { + "udp0": { + "data_width" : 32, + "tx_fifo_depth" : 1024, + "rx_fifo_depth" : 1024, + }, +} diff --git a/liteeth/gen.py b/liteeth/gen.py index 2a0570c..43a05c2 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -284,15 +284,36 @@ class PHYCore(SoCMini): liteeth_phys.USP_GTY_1000BASEX, ]: ethphy_pads = platform.request("sgmii") - ethphy = phy( - refclk_or_clk_pads = ethphy_pads.refclk, - data_pads = ethphy_pads, - sys_clk_freq = self.clk_freq, - refclk_freq = core_config.get("refclk_freq", 200e6), - with_csr = False, - rx_polarity = 0, # Add support to liteeth_gen if useful. - tx_polarity = 0, # Add support to liteeth_gen if useful. - ) + # Artix7. + if phy in [liteeth_phys.A7_1000BASEX]: + assert core_config.get("refclk_freq", 0) == 200e6 + from liteeth.phy.a7_gtp import QPLLSettings, QPLL + qpll_settings = QPLLSettings( + refclksel = 0b001, + fbdiv = 4, + fbdiv_45 = 5, + refclk_div = 1 + ) + qpll = QPLL(ethphy_pads.refclk, qpll_settings) + ethphy = phy( + qpll_channel = qpll.channels[0], + data_pads = ethphy_pads, + sys_clk_freq = self.clk_freq, + with_csr = False, + rx_polarity = 0, # Add support to liteeth_gen if useful. + tx_polarity = 0, # Add support to liteeth_gen if useful. + ) + # Other 7-Series/Ultrascale(+). + else: + ethphy = phy( + refclk_or_clk_pads = ethphy_pads.refclk, + data_pads = ethphy_pads, + sys_clk_freq = self.clk_freq, + refclk_freq = core_config.get("refclk_freq", 200e6), + with_csr = False, + rx_polarity = 0, # Add support to liteeth_gen if useful. + tx_polarity = 0, # Add support to liteeth_gen if useful. + ) self.comb += [ ethphy.reset.eq(ethphy_pads.rst), ethphy_pads.link_up.eq(ethphy.link_up),