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liteeth_gen: Add specific A7_1000BASEX support and example configuration. 

Adapted from known working targets but untested on hardware.
This commit is contained in:
Florent Kermarrec 2024-01-18 13:27:32 +01:00
parent 1ea28bd93a
commit c05de191e2
2 changed files with 56 additions and 9 deletions
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26
examples/udp_a7_gtp_sgmii.yml Normal file
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@ -0,0 +1,26 @@
#
# This file is part of LiteEth.
#
# Copyright (c) 2020-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# PHY ----------------------------------------------------------------------
phy : A7_1000BASEX
vendor : xilinx
toolchain : vivado
# Core ---------------------------------------------------------------------
refclk_freq : 200e6
clk_freq : 25e6
core : udp
data_width : 32
dhcp : True
# UDP Ports --------------------------------------------------------------------
udp_ports: {
"udp0": {
"data_width" : 32,
"tx_fifo_depth" : 1024,
"rx_fifo_depth" : 1024,
},
}

39
liteeth/gen.py
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@ -284,15 +284,36 @@ class PHYCore(SoCMini):
liteeth_phys.USP_GTY_1000BASEX,
]:
ethphy_pads = platform.request("sgmii")
ethphy = phy(
refclk_or_clk_pads = ethphy_pads.refclk,
data_pads = ethphy_pads,
sys_clk_freq = self.clk_freq,
refclk_freq = core_config.get("refclk_freq", 200e6),
with_csr = False,
rx_polarity = 0, # Add support to liteeth_gen if useful.
tx_polarity = 0, # Add support to liteeth_gen if useful.
)
# Artix7.
if phy in [liteeth_phys.A7_1000BASEX]:
assert core_config.get("refclk_freq", 0) == 200e6
from liteeth.phy.a7_gtp import QPLLSettings, QPLL
qpll_settings = QPLLSettings(
refclksel = 0b001,
fbdiv = 4,
fbdiv_45 = 5,
refclk_div = 1
)
qpll = QPLL(ethphy_pads.refclk, qpll_settings)
ethphy = phy(
qpll_channel = qpll.channels[0],
data_pads = ethphy_pads,
sys_clk_freq = self.clk_freq,
with_csr = False,
rx_polarity = 0, # Add support to liteeth_gen if useful.
tx_polarity = 0, # Add support to liteeth_gen if useful.
)
# Other 7-Series/Ultrascale(+).
else:
ethphy = phy(
refclk_or_clk_pads = ethphy_pads.refclk,
data_pads = ethphy_pads,
sys_clk_freq = self.clk_freq,
refclk_freq = core_config.get("refclk_freq", 200e6),
with_csr = False,
rx_polarity = 0, # Add support to liteeth_gen if useful.
tx_polarity = 0, # Add support to liteeth_gen if useful.
)
self.comb += [
ethphy.reset.eq(ethphy_pads.rst),
ethphy_pads.link_up.eq(ethphy.link_up),