From c16e6b2d86839dfe0d887e5282dbaddf67a851ae Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Fri, 17 Jan 2020 12:45:37 -0800 Subject: [PATCH] phy/ecp5rgmii.py: Missed moving dw as class variable here --- liteeth/phy/ecp5rgmii.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/liteeth/phy/ecp5rgmii.py b/liteeth/phy/ecp5rgmii.py index cf978b4..823c839 100644 --- a/liteeth/phy/ecp5rgmii.py +++ b/liteeth/phy/ecp5rgmii.py @@ -175,8 +175,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR): + dw = 8 + def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): - self.dw = 8 self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, tx_delay))