From c1783ce554dbd7a74c3968cee584189cf63b1af0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 23 Nov 2019 19:49:23 +0100 Subject: [PATCH] examples/targets: update and cleanup --- examples/targets/Makefile | 6 +- examples/targets/base.py | 163 +++++++++++++++------------------- examples/targets/core.py | 65 +++++++------- examples/targets/etherbone.py | 12 +-- examples/targets/tty.py | 10 ++- examples/targets/udp.py | 10 ++- 6 files changed, 128 insertions(+), 138 deletions(-) diff --git a/examples/targets/Makefile b/examples/targets/Makefile index 16e8839..3fcda6d 100644 --- a/examples/targets/Makefile +++ b/examples/targets/Makefile @@ -2,11 +2,11 @@ cores: rm -rf cores mkdir cores - python3 core.py --phy MII --core mac + python3 core.py --phy MII --core wishbone cp liteeth/gateware/liteeth.v cores/liteeth_mac_mii.v - python3 core.py --phy GMII --core mac + python3 core.py --phy GMII --core wishbone cp liteeth/gateware/liteeth.v cores/liteeth_mac_gmii.v - python3 core.py --phy RGMII --core mac + python3 core.py --phy RGMII --core wishbone cp liteeth/gateware/liteeth.v cores/liteeth_mac_rgmii.v python3 core.py --phy MII --core udp diff --git a/examples/targets/base.py b/examples/targets/base.py index d9f2bbc..905c295 100644 --- a/examples/targets/base.py +++ b/examples/targets/base.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2015-2018 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from migen.genlib.io import CRG @@ -13,129 +13,108 @@ from liteeth.common import * from liteeth.phy import LiteEthPHY from liteeth.core import LiteEthUDPIPCore +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - csr_map = { - "phy": 11, - "core": 12 - } - csr_map.update(SoCCore.csr_map) - def __init__(self, platform, clk_freq=166*1000000, - mac_address=0x10e2d5000000, - ip_address="192.168.1.50"): - clk_freq = int((1/(platform.default_clk_period))*1000000000) + def __init__(self, platform, clk_freq=int(166e6), + mac_address = 0x10e2d5000000, + ip_address = "192.168.1.50"): + sys_clk_freq = int((1/(platform.default_clk_period))*1e9) SoCCore.__init__(self, platform, clk_freq, - cpu_type=None, - csr_data_width=32, - with_uart=False, - ident="LiteEth Base Design", - with_timer=False + cpu_type = None, + csr_data_width = 32, + with_uart = False, + ident = "LiteEth Base Design", + with_timer = False ) - self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200) - self.add_wb_master(self.bridge.wishbone) + + # Serial Wishbone Bridge + serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200) + self.submodules += serial_bridge + self.add_wb_master(serial_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) - # wishbone SRAM (to test Wishbone over UART and Etherbone) + # Wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) - # ethernet PHY and UDP/IP stack - self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) - self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq) + # Ethernet PHY and UDP/IP stack + self.submodules.ethphy = ethphy = LiteEthPHY( + clock_pads = platform.request("eth_clocks"), + pads = platform.request("eth"), + clk_freq = clk_freq) + self.add_csr("ethphy") + self.submodules.ethcore = ethcore = LiteEthUDPIPCore( + phy = ethphy, + mac_address = mac_address, + ip_address = ip_address, + clk_freq = clk_freq) + self.add_csr("ethcore") if isinstance(platform.toolchain, XilinxVivadoToolchain): self.crg.cd_sys.clk.attr.add("keep") - self.phy.crg.cd_eth_rx.clk.attr.add("keep") - self.phy.crg.cd_eth_tx.clk.attr.add("keep") - platform.add_platform_command(""" -create_clock -name sys_clk -period 6.0 [get_nets sys_clk] -create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk] -create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk] -set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk] -set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk] -set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk] -set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] -""") + ethphy.crg.cd_eth_rx.clk.attr.add("keep") + ethphy.crg.cd_eth_tx.clk.attr.add("keep") + platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) + platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + ethphy.crg.cd_eth_rx.clk, + ethphy.crg.cd_eth_tx.clk) +# BaseSoCDevel ------------------------------------------------------------------------------------- class BaseSoCDevel(BaseSoC): def __init__(self, platform): from litescope import LiteScopeAnalyzer BaseSoC.__init__(self, platform) - self.core_icmp_rx_fsm_state = Signal(4) - self.core_icmp_tx_fsm_state = Signal(4) - self.core_udp_rx_fsm_state = Signal(4) - self.core_udp_tx_fsm_state = Signal(4) - self.core_ip_rx_fsm_state = Signal(4) - self.core_ip_tx_fsm_state = Signal(4) - self.core_arp_rx_fsm_state = Signal(4) - self.core_arp_tx_fsm_state = Signal(4) - self.core_arp_table_fsm_state = Signal(4) - - debug = [ + analyzer_signals = [ # MAC interface - self.core.mac.core.sink.valid, - self.core.mac.core.sink.last, - self.core.mac.core.sink.ready, - self.core.mac.core.sink.data, + self.ethcore.mac.core.sink.valid, + self.ethcore.mac.core.sink.last, + self.ethcore.mac.core.sink.ready, + self.ethcore.mac.core.sink.data, - self.core.mac.core.source.valid, - self.core.mac.core.source.last, - self.core.mac.core.source.ready, - self.core.mac.core.source.data, + self.ethcore.mac.core.source.valid, + self.ethcore.mac.core.source.last, + self.ethcore.mac.core.source.ready, + self.ethcore.mac.core.source.data, # ICMP interface - self.core.icmp.echo.sink.valid, - self.core.icmp.echo.sink.last, - self.core.icmp.echo.sink.ready, - self.core.icmp.echo.sink.data, + self.ethcore.icmp.echo.sink.valid, + self.ethcore.icmp.echo.sink.last, + self.ethcore.icmp.echo.sink.ready, + self.ethcore.icmp.echo.sink.data, - self.core.icmp.echo.source.valid, - self.core.icmp.echo.source.last, - self.core.icmp.echo.source.ready, - self.core.icmp.echo.source.data, + self.ethcore.icmp.echo.source.valid, + self.ethcore.icmp.echo.source.last, + self.ethcore.icmp.echo.source.ready, + self.ethcore.icmp.echo.source.data, # IP interface - self.core.ip.crossbar.master.sink.valid, - self.core.ip.crossbar.master.sink.last, - self.core.ip.crossbar.master.sink.ready, - self.core.ip.crossbar.master.sink.data, - self.core.ip.crossbar.master.sink.ip_address, - self.core.ip.crossbar.master.sink.protocol, + self.ethcore.ip.crossbar.master.sink.valid, + self.ethcore.ip.crossbar.master.sink.last, + self.ethcore.ip.crossbar.master.sink.ready, + self.ethcore.ip.crossbar.master.sink.data, + self.ethcore.ip.crossbar.master.sink.ip_address, + self.ethcore.ip.crossbar.master.sink.protocol, # State machines - self.core_icmp_rx_fsm_state, - self.core_icmp_tx_fsm_state, + self.ethcore.icmp.rx.fsm, + self.ethcore.icmp.tx.fsm, - self.core_arp_rx_fsm_state, - self.core_arp_tx_fsm_state, - self.core_arp_table_fsm_state, + self.ethcore.arp.rx.fsm, + self.ethcore.arp.tx.fsm, + self.ethcore.arp.table.fsm, - self.core_ip_rx_fsm_state, - self.core_ip_tx_fsm_state, + self.ethcore.ip.rx.fsm, + self.ethcore.ip.tx.fsm, - self.core_udp_rx_fsm_state, - self.core_udp_tx_fsm_state + self.ethcore.udp.rx.fsm, + self.ethcore.udp.tx.fsm ] - self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096, csr_csv="test/analyzer.csv") + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="test/analyzer.csv") self.add_csr("analyzer") - def do_finalize(self): - BaseSoC.do_finalize(self) - self.comb += [ - self.core_icmp_rx_fsm_state.eq(self.core.icmp.rx.fsm.state), - self.core_icmp_tx_fsm_state.eq(self.core.icmp.tx.fsm.state), - - self.core_arp_rx_fsm_state.eq(self.core.arp.rx.fsm.state), - self.core_arp_tx_fsm_state.eq(self.core.arp.tx.fsm.state), - self.core_arp_table_fsm_state.eq(self.core.arp.table.fsm.state), - - self.core_ip_rx_fsm_state.eq(self.core.ip.rx.fsm.state), - self.core_ip_tx_fsm_state.eq(self.core.ip.tx.fsm.state), - - self.core_udp_rx_fsm_state.eq(self.core.udp.rx.fsm.state), - self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state) - ] - default_subtarget = BaseSoC diff --git a/examples/targets/core.py b/examples/targets/core.py index d27e485..b24be77 100644 --- a/examples/targets/core.py +++ b/examples/targets/core.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 -# This file is Copyright (c) 2015-2018 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD import argparse @@ -24,6 +24,8 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII from liteeth.mac import LiteEthMAC from liteeth.core import LiteEthUDPIPCore +# IOs ---------------------------------------------------------------------------------------------- + _io = [ ("sys_clock", 0, Pins(1)), ("sys_reset", 1, Pins(1)), @@ -142,6 +144,8 @@ _io = [ ), ] +# Platform ----------------------------------------------------------------------------------------- + class CorePlatform(XilinxPlatform): name = "core" def __init__(self): @@ -150,6 +154,7 @@ class CorePlatform(XilinxPlatform): def do_finalize(self, *args, **kwargs): pass +# PHY Core ----------------------------------------------------------------------------------------- class PHYCore(SoCCore): def __init__(self, phy, clk_freq): @@ -166,29 +171,25 @@ class PHYCore(SoCCore): platform.request("sys_reset")) # ethernet if phy == "MII": - self.submodules.ethphy = LiteEthPHYMII(platform.request("mii_eth_clocks"), - platform.request("mii_eth")) + ethphy = LiteEthPHYMII(platform.request("mii_eth_clocks"), + platform.request("mii_eth")) elif phy == "RMII": - self.submodules.ethphy = LiteEthPHYRMII(platform.request("rmii_eth_clocks"), - platform.request("rmii_eth")) + ethphy = LiteEthPHYRMII(platform.request("rmii_eth_clocks"), + platform.request("rmii_eth")) elif phy == "GMII": - self.submodules.ethphy = LiteEthPHYGMII(platform.request("gmii_eth_clocks"), - platform.request("gmii_eth")) + ethphy = LiteEthPHYGMII(platform.request("gmii_eth_clocks"), + platform.request("gmii_eth")) elif phy == "RGMII": - self.submodules.ethphy = LiteEthPHYRGMII(platform.request("rgmii_eth_clocks"), - platform.request("rgmii_eth")) + ethphy = LiteEthPHYRGMII(platform.request("rgmii_eth_clocks"), + platform.request("rgmii_eth")) else: ValueError("Unsupported " + phy + " PHY"); + self.submodules.ethphy = ethphy + self.add_csr("ethphy") +# MAC Core ----------------------------------------------------------------------------------------- class MACCore(PHYCore): - csr_peripherals = ( - "ethphy", - "ethmac" - ) - csr_map = dict((n, v) for v, n in enumerate(csr_peripherals, start=16)) - csr_map.update(SoCCore.csr_map) - interrupt_map = { "ethmac": 2, } @@ -204,15 +205,18 @@ class MACCore(PHYCore): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_csr("ethmac") class _WishboneBridge(Module): def __init__(self, interface): self.wishbone = interface - self.add_cpu(_WishboneBridge(self.platform.request("wishbone"))) - self.add_wb_master(self.cpu.wishbone) + bridge = _WishboneBridge(self.platform.request("wishbone")) + self.submodules += bridge + self.add_wb_master(bridge.wishbone) +# UDP Core ----------------------------------------------------------------------------------------- class UDPCore(PHYCore): def __init__(self, phy, clk_freq, mac_address, ip_address, port): @@ -223,39 +227,40 @@ class UDPCore(PHYCore): # XXX avoid manual connect udp_sink = self.platform.request("udp_sink") self.comb += [ - # control + # Control udp_port.sink.valid.eq(udp_sink.valid), udp_port.sink.last.eq(udp_sink.last), udp_sink.ready.eq(udp_port.sink.ready), - # param + # Param udp_port.sink.src_port.eq(udp_sink.src_port), udp_port.sink.dst_port.eq(udp_sink.dst_port), udp_port.sink.ip_address.eq(udp_sink.ip_address), udp_port.sink.length.eq(udp_sink.length), - # payload + # Payload udp_port.sink.data.eq(udp_sink.data), udp_port.sink.error.eq(udp_sink.error) ] udp_source = self.platform.request("udp_source") self.comb += [ - # control + # Control udp_source.valid.eq(udp_port.source.valid), udp_source.last.eq(udp_port.source.last), udp_port.source.ready.eq(udp_source.ready), - # param + # Param udp_source.src_port.eq(udp_port.source.src_port), udp_source.dst_port.eq(udp_port.source.dst_port), udp_source.ip_address.eq(udp_port.source.ip_address), udp_source.length.eq(udp_port.source.length), - # payload + # Payload udp_source.data.eq(udp_port.source.data), udp_source.error.eq(udp_port.source.error) ] +# Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteEth core builder") @@ -268,12 +273,12 @@ def main(): args = parser.parse_args() if args.core == "wishbone": - soc = MACCore(phy=args.phy, clk_freq=100*1000000) + soc = MACCore(phy=args.phy, clk_freq=int(100e6)) elif args.core == "udp": - soc = UDPCore(phy=args.phy, clk_freq=100*10000000, - mac_address=args.mac_address, - ip_address=args.ip_address, - port=6000) + soc = UDPCore(phy=args.phy, clk_freq=int(100e6), + mac_address = args.mac_address, + ip_address = args.ip_address, + port = 6000) else: raise ValueError builder = Builder(soc, output_dir="liteeth", compile_gateware=False, csr_csv="liteeth/csr.csv") diff --git a/examples/targets/etherbone.py b/examples/targets/etherbone.py index e8f2d45..4bc6791 100644 --- a/examples/targets/etherbone.py +++ b/examples/targets/etherbone.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2015-2018 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from liteeth.common import * @@ -6,6 +6,7 @@ from liteeth.frontend.etherbone import LiteEthEtherbone from targets.base import BaseSoC +# EtherboneSoC ------------------------------------------------------------------------------------- class EtherboneSoC(BaseSoC): default_platform = "kc705" @@ -13,16 +14,17 @@ class EtherboneSoC(BaseSoC): BaseSoC.__init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50") - self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, mode="master") + self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) +# EtherboneSoCDevel -------------------------------------------------------------------------------- class EtherboneSoCDevel(EtherboneSoC): def __init__(self, platform): from litescope import LiteScopeAnalyzer EtherboneSoC.__init__(self, platform) debug = [ - # mmap stream from HOST + # MMAP stream from HOST self.etherbone.wishbone.sink.valid, self.etherbone.wishbone.sink.last, self.etherbone.wishbone.sink.ready, @@ -33,7 +35,7 @@ class EtherboneSoCDevel(EtherboneSoC): self.etherbone.wishbone.sink.addr, self.etherbone.wishbone.sink.data, - # mmap stream to HOST + # MMAP stream to HOST self.etherbone.wishbone.source.valid, self.etherbone.wishbone.source.last, self.etherbone.wishbone.source.ready, @@ -44,7 +46,7 @@ class EtherboneSoCDevel(EtherboneSoC): self.etherbone.wishbone.source.addr, self.etherbone.wishbone.source.data, - # etherbone wishbone master + # Etherbone wishbone master self.etherbone.wishbone.bus.dat_w, self.etherbone.wishbone.bus.dat_r, self.etherbone.wishbone.bus.adr, diff --git a/examples/targets/tty.py b/examples/targets/tty.py index 1e234a6..6b68db9 100644 --- a/examples/targets/tty.py +++ b/examples/targets/tty.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2015-2018 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from liteeth.common import * @@ -6,6 +6,7 @@ from liteeth.frontend.tty import LiteEthTTY from targets.base import BaseSoC +# TTYSoC ------------------------------------------------------------------------------------------- class TTYSoC(BaseSoC): default_platform = "kc705" @@ -13,15 +14,16 @@ class TTYSoC(BaseSoC): BaseSoC.__init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50") - self.submodules.tty = LiteEthTTY(self.core.udp, convert_ip("192.168.1.100"), 10000) + self.submodules.tty = LiteEthTTY(self.ethcore.udp, convert_ip("192.168.1.100"), 10000) self.comb += self.tty.source.connect(self.tty.sink) +# TTYSoDevel --------------------------------------------------------------------------------------- class TTYSoCDevel(TTYSoC): def __init__(self, platform): from litescope import LiteScopeAnalyzer TTYSoC.__init__(self, platform) - debug = [ + analyzer_signals = [ self.tty.sink.valid, self.tty.sink.ready, self.tty.sink.data, @@ -30,7 +32,7 @@ class TTYSoCDevel(TTYSoC): self.tty.source.ready, self.tty.source.data ] - self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096, csr_csv="test/analyzer.csv") + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="test/analyzer.csv") self.add_csr("analyzer") default_subtarget = TTYSoC diff --git a/examples/targets/udp.py b/examples/targets/udp.py index 6804ac0..2b17150 100644 --- a/examples/targets/udp.py +++ b/examples/targets/udp.py @@ -1,10 +1,11 @@ -# This file is Copyright (c) 2015-2018 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from liteeth.common import * from targets.base import BaseSoC +# UDPSoC ------------------------------------------------------------------------------------------- class UDPSoC(BaseSoC): default_platform = "kc705" @@ -19,7 +20,7 @@ class UDPSoC(BaseSoC): self.add_udp_loopback(8000, 32, 8192, "loopback_32") def add_udp_loopback(self, port, dw, depth, name=None): - port = self.core.udp.crossbar.get_port(port, dw) + port = self.ethcore.udp.crossbar.get_port(port, dw) buf = stream.SyncFIFO(eth_udp_user_description(dw), depth//(dw//8)) if name is None: self.submodules += buf @@ -27,12 +28,13 @@ class UDPSoC(BaseSoC): setattr(self.submodules, name, buf) self.comb += Port.connect(port, buf) +# UDPSoCDevel -------------------------------------------------------------------------------------- class UDPSoCDevel(UDPSoC): def __init__(self, platform): from litescope import LiteScopeAnalyzer UDPSoC.__init__(self, platform) - debug = [ + analyzer_signals = [ self.loopback_8.sink.valid, self.loopback_8.sink.last, self.loopback_8.sink.ready, @@ -53,7 +55,7 @@ class UDPSoCDevel(UDPSoC): self.loopback_32.source.ready, self.loopback_32.source.data ] - self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096, csr_csv="test/analyzer.csv") + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="test/analyzer.csv") self.add_csr("analyzer") default_subtarget = UDPSoC