enjoy-digital
GitHub
commit
c1dc02093d
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@ -1,98 +1,78 @@
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015-2024 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2021 David Sawatzke <d-git@sawatzke.dev>
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# Copyright (c) 2017 whitequark <whitequark@whitequark.org>
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# Copyright (c) 2018 Felix Held <felix-github@felixheld.de>
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# SPDX-License-Identifier: BSD-2-Clause
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from functools import reduce
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from operator import xor
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from collections import OrderedDict
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from math import ceil
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from litex.gen import *
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from liteeth.common import *
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from litex.gen.genlib.misc import chooser, WaitTimer
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# MAC CRC Engine -----------------------------------------------------------------------------------
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class LiteEthMACCRCEngine(Module):
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"""Cyclic Redundancy Check Engine
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class LiteEthMACCRCEngine(LiteXModule):
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"""
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Cyclic Redundancy Check (CRC) Engine using an asynchronous LFSR.
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Compute next CRC value from last CRC value and data input using
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an optimized asynchronous LFSR.
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This module calculates the next CRC value based on the previous CRC value and the current data input.
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The CRC calculation is optimized for speed and resource efficiency.
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Parameters
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----------
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data_width : int
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Width of the data bus.
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width : int
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Width of the CRC.
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The bit width of the data bus and CRC value.
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polynom : int
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Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
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Attributes
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----------
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data : in
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Data input.
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last : in
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last CRC value.
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next :
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next CRC value.
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The polynomial used for the CRC calculation, specified as an integer (e.g., 0x04C11DB7 for IEEE 802.3).
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"""
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def __init__(self, data_width, width, polynom):
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self.data = Signal(data_width)
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self.last = Signal(width)
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self.next = Signal(width)
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self.data = Signal(data_width) # Data (Input).
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self.crc_prev = Signal(width) # CRC Previous (Input).
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self.crc_next = Signal(width) # CRC Next (Output).
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# # #
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def _optimize_eq(l):
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"""
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remove an even numbers of XORs with the same bit
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replace an odd number of XORs with a single XOR
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"""
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d = OrderedDict()
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for e in l:
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if e in d:
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d[e] += 1
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else:
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d[e] = 1
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r = []
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for key, value in d.items():
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if value%2 != 0:
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r.append(key)
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return r
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# Determine bits affected by the polynom.
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polynom_taps = [bit for bit in range(width) if (1 << bit) & polynom]
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# compute and optimize the parallel implementation of the CRC's LFSR
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taps = [x for x in range(width) if (1 << x) & polynom]
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curval = [[("state", i)] for i in range(width)]
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for i in range(data_width):
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feedback = curval.pop() + [("din", i)]
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for j in range(width-1):
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if j+1 in taps:
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curval[j] += feedback
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curval[j] = _optimize_eq(curval[j])
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curval.insert(0, feedback)
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# Prepare the list for CRC calculation through LFSR.
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crc_bits = [[("state", i)] for i in range(width)]
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for n in range(data_width):
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feedback = crc_bits.pop(-1) + [("din", n)]
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for pos in range(width - 1):
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if (pos + 1) in polynom_taps:
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crc_bits[pos] += feedback
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crc_bits[pos] = self.optimize_xors(crc_bits[pos])
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crc_bits.insert(0, feedback)
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# implement logic
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# Calculate the next CRC value based on XOR operations.
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for i in range(width):
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xors = []
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for t, n in curval[i]:
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for t, n in crc_bits[i]:
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if t == "state":
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xors += [self.last[n]]
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xors += [self.crc_prev[n]]
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elif t == "din":
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xors += [self.data[n]]
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self.comb += self.next[i].eq(reduce(xor, xors))
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self.comb += self.crc_next[i].eq(Reduce("XOR", xors))
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@staticmethod
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def optimize_xors(bits):
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"""Return items with odd occurrences for XOR optimization."""
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from collections import Counter
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return [bit for bit, count in Counter(bits).items() if count % 2 == 1]
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# MAC CRC32 ----------------------------------------------------------------------------------------
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@ResetInserter()
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@CEInserter()
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class LiteEthMACCRC32(Module):
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class LiteEthMACCRC32(LiteXModule):
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"""IEEE 802.3 CRC
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Implement an IEEE 802.3 CRC generator/checker.
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@ -106,52 +86,50 @@ class LiteEthMACCRC32(Module):
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----------
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data : in
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Data input.
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last_be : in
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Valid byte in data input (optional).
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be : in
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Data byte enable (optional, defaults to full word).
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value : out
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CRC value (used for generator).
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error : out
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CRC error (used for checker).
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"""
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width = 32
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polynom = 0x04C11DB7
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polynom = 0x04c11db7
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init = 2**width-1
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check = 0xC704DD7B
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check = 0xc704dd7b
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def __init__(self, data_width):
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dw = data_width//8
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self.data = Signal(data_width)
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self.last_be = Signal(dw)
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self.value = Signal(self.width)
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self.error = Signal()
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# Add a separate last_be signal, to maintain backwards compatability
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last_be = Signal(data_width//8)
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self.data = Signal(data_width)
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self.be = Signal(data_width//8, reset=2**data_width//8 - 1)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.comb += [
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If(self.last_be != 0,
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last_be.eq(self.last_be)
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).Else(
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last_be.eq(2**(dw-1)))
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]
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# Since the data can end at any byte end, indicated by `last_be`
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# maintain separate engines for each 8 byte increment in the data word
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engines = [LiteEthMACCRCEngine((e+1)*8, self.width, self.polynom) for e in range(dw)]
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# Create a CRC Engine for each byte segment.
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# Ex for a 32-bit Data-Path, we create 4 engines: 8, 16, 24 and 32-bit engines.
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engines = []
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for n in range(data_width//8):
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engines.append(LiteEthMACCRCEngine((n + 1)*8, self.width, self.polynom))
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self.submodules += engines
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# Register Full-Word CRC Engine (last one).
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reg = Signal(self.width, reset=self.init)
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self.sync += reg.eq(engines[-1].next)
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self.comb += [engines[e].data.eq(self.data[:(e+1)*8]) for e in range(dw)],
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self.comb += [engines[e].last.eq(reg) for e in range(dw)]
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self.comb += [If(last_be[e],
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self.value.eq(reverse_bits(~engines[e].next)),
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self.error.eq(engines[e].next != self.check))
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for e in range(dw)]
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self.sync += reg.eq(engines[-1].crc_next)
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# MAC CRC Inserter ---------------------------------------------------------------------------------
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# Select CRC Engine/Result.
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for n in range(data_width//8):
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self.comb += [
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engines[n].data.eq(self.data[:(n + 1)*8]),
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engines[n].crc_prev.eq(reg),
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If(self.be[n],
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self.value.eq(reverse_bits(~engines[n].crc_next)),
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self.error.eq(engines[n].crc_next != self.check),
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)
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]
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class LiteEthMACCRCInserter(Module):
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# MAC CRC32 Inserter -------------------------------------------------------------------------------
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class LiteEthMACCRC32Inserter(LiteXModule):
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"""CRC Inserter
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Append a CRC at the end of each packet.
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@ -168,22 +146,26 @@ class LiteEthMACCRCInserter(Module):
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source : out
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Packet data with CRC.
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"""
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def __init__(self, crc_class, description):
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self.sink = sink = stream.Endpoint(description)
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def __init__(self, description):
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self.sink = sink = stream.Endpoint(description)
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self.source = source = stream.Endpoint(description)
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# # #
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dw = len(sink.data)
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assert dw in [8, 32, 64]
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crc = crc_class(dw)
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fsm = FSM(reset_state="IDLE")
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self.submodules += crc, fsm
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# Parameters.
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data_width = len(sink.data)
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ratio = 32//data_width
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assert data_width in [8, 32, 64]
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# crc packet checksum
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crc_packet = Signal(crc.width)
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last_be = Signal().like(sink.last_be)
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# Signals.
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crc_packet = Signal(32)
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last_be = Signal(data_width//8)
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# CRC32 Generator.
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self.crc = crc = LiteEthMACCRC32(data_width)
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# FSM.
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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crc.reset.eq(1),
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sink.ready.eq(1),
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@ -192,35 +174,36 @@ class LiteEthMACCRCInserter(Module):
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NextState("COPY"),
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)
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)
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self.comb += [
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crc.data.eq(sink.data),
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crc.be.eq(sink.last_be),
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]
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fsm.act("COPY",
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crc.ce.eq(sink.valid & source.ready),
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crc.data.eq(sink.data),
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crc.last_be.eq(sink.last_be),
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sink.connect(source),
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source.last.eq(0),
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source.last_be.eq(0),
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If(sink.last,
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# Fill the empty space of the last data word with the
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# beginning of the crc value
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# Fill the empty space of the last data word with the beginning of the CRC value.
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[If(sink.last_be[e],
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source.data.eq(Cat(sink.data[:(e+1)*8],
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crc.value)[:dw])) for e in range(dw//8)],
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# If the whole crc value fits in the last sink paket, signal the
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# end. This also means the next state is idle
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If((dw == 64) & (sink.last_be <= 0xF),
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crc.value)[:data_width])) for e in range(data_width//8)],
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# If the whole crc value fits in the last sink packet, signal the end. This also
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# means the next state is idle
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If((data_width == 64) & (sink.last_be <= 0xf),
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source.last.eq(1),
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source.last_be.eq(sink.last_be << (dw//8 - 4))
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source.last_be.eq(sink.last_be << (data_width//8 - 4))
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),
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).Else(
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crc.ce.eq(sink.valid & source.ready),
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),
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If(sink.valid & sink.last & source.ready,
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If((dw == 64) & (sink.last_be <= 0xF),
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If((data_width == 64) & (sink.last_be <= 0xf),
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NextState("IDLE"),
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).Else(
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NextValue(crc_packet, crc.value),
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If(dw == 64,
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If(data_width == 64,
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NextValue(last_be, sink.last_be >> 4),
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).Else (
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NextValue(last_be, sink.last_be),
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@ -229,16 +212,17 @@ class LiteEthMACCRCInserter(Module):
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)
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)
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)
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ratio = crc.width//dw
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if ratio > 1:
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cnt = Signal(max=ratio, reset=ratio-1)
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cnt = Signal(max=ratio, reset=ratio-1)
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cnt_done = Signal()
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fsm.act("CRC",
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source.valid.eq(1),
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chooser(crc_packet, cnt, source.data, reverse=True),
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If(cnt_done,
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source.last.eq(1),
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If(source.ready, NextState("IDLE"))
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If(source.ready,
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NextState("IDLE")
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)
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)
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)
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self.comb += cnt_done.eq(cnt == 0)
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@ -255,18 +239,15 @@ class LiteEthMACCRCInserter(Module):
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source.data.eq(crc.value),
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source.last_be.eq(last_be),
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[If(last_be[e],
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source.data.eq(crc_packet[-(e+1)*8:])) for e in range(dw//8)],
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If(source.ready, NextState("IDLE"))
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source.data.eq(crc_packet[-(e+1)*8:])) for e in range(data_width//8)],
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If(source.ready,
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NextState("IDLE")
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)
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)
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# MAC CRC32 Checker --------------------------------------------------------------------------------
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class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
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def __init__(self, description):
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LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description)
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# MAC CRC Checker ----------------------------------------------------------------------------------
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class LiteEthMACCRCChecker(Module):
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class LiteEthMACCRC32Checker(LiteXModule):
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"""CRC Checker
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Check CRC at the end of each packet.
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@ -286,7 +267,7 @@ class LiteEthMACCRCChecker(Module):
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error : out
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Pulses every time a CRC error is detected.
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"""
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def __init__(self, crc_class, description):
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def __init__(self, description):
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self.sink = sink = stream.Endpoint(description)
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self.source = source = stream.Endpoint(description)
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@ -294,17 +275,16 @@ class LiteEthMACCRCChecker(Module):
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# # #
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dw = len(sink.data)
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assert dw in [8, 32, 64]
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crc = crc_class(dw)
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self.submodules += crc
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ratio = ceil(crc.width/dw)
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# Parameters.
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data_width = len(sink.data)
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ratio = ceil(32/data_width)
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assert data_width in [8, 32, 64]
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fifo = ResetInserter()(stream.SyncFIFO(description, ratio + 1))
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self.submodules += fifo
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# CRC32 Checker.
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self.crc = crc = LiteEthMACCRC32(data_width)
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fsm = FSM(reset_state="RESET")
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self.submodules += fsm
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# FIFO.
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self.fifo = fifo = ResetInserter()(stream.SyncFIFO(description, ratio + 1))
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fifo_in = Signal()
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fifo_out = Signal()
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@ -320,6 +300,8 @@ class LiteEthMACCRCChecker(Module):
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self.sink.ready.eq(fifo_in),
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]
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# FSM.
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self.fsm = fsm = FSM(reset_state="RESET")
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fsm.act("RESET",
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crc.reset.eq(1),
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fifo.reset.eq(1),
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@ -327,7 +309,7 @@ class LiteEthMACCRCChecker(Module):
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)
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self.comb += [
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crc.data.eq(sink.data),
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crc.last_be.eq(sink.last_be),
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crc.be.eq(sink.last_be),
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]
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fsm.act("IDLE",
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If(sink.valid & sink.ready,
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|
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@ -335,37 +317,37 @@ class LiteEthMACCRCChecker(Module):
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NextState("COPY")
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)
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)
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last_be = Signal().like(sink.last_be)
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last_be = Signal().like(sink.last_be)
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crc_error = Signal()
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self.comb += fifo.source.connect(source, omit={"valid", "ready", "last", "last_be"})
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fsm.act("COPY",
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fifo.source.ready.eq(fifo_out),
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source.valid.eq(sink.valid & fifo_full),
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source.payload.eq(fifo.source.payload),
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If(dw <= 32,
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If(data_width <= 32,
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source.last.eq(sink.last),
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source.last_be.eq(sink.last_be),
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# For dw == 64 bit, we need to look wether the last word contains only the crc value or both crc and data
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# For data_width == 64 bit, we need to look wether the last word contains only the crc value or both crc and data
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# In the latter case, the last word also needs to be output
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# In both cases, last_be needs to be adjusted for the new end position
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).Elif(sink.last_be & 0xF,
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source.last.eq(sink.last),
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source.last_be.eq(sink.last_be << (dw//8 - 4)),
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source.last_be.eq(sink.last_be << (data_width//8 - 4)),
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).Else(
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NextValue(last_be, sink.last_be >> 4),
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NextValue(crc_error, crc.error),
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),
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# `source.error` has a width > 1 for dw > 8, but since the crc error
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# `source.error` has a width > 1 for data_width > 8, but since the crc error
|
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# applies to the whole ethernet packet, all the bytes are marked as
|
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# containing an error. This way later reducing the data width
|
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# doesn't run into issues with missing the error
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source.error.eq(sink.error | Replicate(crc.error & sink.last, dw//8)),
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source.error.eq(sink.error | Replicate(crc.error & sink.last, data_width//8)),
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self.error.eq(sink.valid & sink.last & crc.error),
|
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If(sink.valid & sink.ready,
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crc.ce.eq(1),
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# Can only happen for dw == 64
|
||||
# Can only happen for data_width == 64
|
||||
If(sink.last & (sink.last_be > 0xF),
|
||||
NextState("COPY_LAST"),
|
||||
).Elif(sink.last,
|
||||
|
|
@ -375,17 +357,12 @@ class LiteEthMACCRCChecker(Module):
|
|||
)
|
||||
|
||||
# If the last sink word contains both data and the crc value, shift out
|
||||
# the last value here. Can only happen for dw == 64
|
||||
# the last value here. Can only happen for data_width == 64
|
||||
fsm.act("COPY_LAST",
|
||||
fifo.source.connect(source),
|
||||
source.error.eq(fifo.source.error | Replicate(crc_error, dw//8)),
|
||||
fifo.source.connect(source, keep={"valid", "ready", "last"}),
|
||||
source.error.eq(fifo.source.error | Replicate(crc_error, data_width//8)),
|
||||
source.last_be.eq(last_be),
|
||||
If(source.valid & source.ready,
|
||||
NextState("RESET")
|
||||
)
|
||||
)
|
||||
|
||||
|
||||
class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):
|
||||
def __init__(self, description):
|
||||
LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description)
|
||||
|
|
|
|||
Loading…
Reference in New Issue