From c3b985036670d8bc2dc8edb18ec67dede29b9f5c Mon Sep 17 00:00:00 2001 From: David Sawatzke Date: Sun, 8 Aug 2021 22:25:21 +0200 Subject: [PATCH] liteeth/core: Allow configuration of full_mem_we parameter --- liteeth/gen.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 9b62b75..df467f9 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -219,12 +219,13 @@ class MACCore(PHYCore): # MAC -------------------------------------------------------------------------------------- self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = core_config["endianness"], - nrxslots = nrxslots, - ntxslots = ntxslots) + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = core_config["endianness"], + nrxslots = nrxslots, + ntxslots = ntxslots, + full_memory_we = core_config.get("full_memory_we", False)) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io") self.add_csr("ethmac")