diff --git a/liteeth/core/mac/core/__init__.py b/liteeth/core/mac/core/__init__.py
index 595890a..96a4d8e 100644
--- a/liteeth/core/mac/core/__init__.py
+++ b/liteeth/core/mac/core/__init__.py
@@ -1,8 +1,6 @@
 from liteeth.common import *
 from liteeth.core.mac.core import gap, preamble, crc, padding, last_be
 from liteeth.phy.model import LiteEthPHYModel
-from liteeth.phy.mii import LiteEthPHYMII
-from liteeth.phy.rmii import LiteEthPHYRMII
 
 
 class LiteEthMACCore(Module, AutoCSR):
@@ -82,12 +80,8 @@ class LiteEthMACCore(Module, AutoCSR):
             rx_pipeline += [rx_converter]
 
         # Cross Domain Crossing
-        if isinstance(phy, (LiteEthPHYMII, LiteEthPHYRMII)):
-            fifo_depth = 8
-        else:
-            fifo_depth = 64
-        tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
-        rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
+        tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64)
+        rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64)
         self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
         self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)