From c3e15e7f7b3aba6619c1733114f6ea43ea413218 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 Mar 2016 19:41:53 +0100 Subject: [PATCH] core/mac: use fifo_depth of 64 for all phys --- liteeth/core/mac/core/__init__.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/liteeth/core/mac/core/__init__.py b/liteeth/core/mac/core/__init__.py index 595890a..96a4d8e 100644 --- a/liteeth/core/mac/core/__init__.py +++ b/liteeth/core/mac/core/__init__.py @@ -1,8 +1,6 @@ from liteeth.common import * from liteeth.core.mac.core import gap, preamble, crc, padding, last_be from liteeth.phy.model import LiteEthPHYModel -from liteeth.phy.mii import LiteEthPHYMII -from liteeth.phy.rmii import LiteEthPHYRMII class LiteEthMACCore(Module, AutoCSR): @@ -82,12 +80,8 @@ class LiteEthMACCore(Module, AutoCSR): rx_pipeline += [rx_converter] # Cross Domain Crossing - if isinstance(phy, (LiteEthPHYMII, LiteEthPHYRMII)): - fifo_depth = 8 - else: - fifo_depth = 64 - tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth) - rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth) + tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64) + rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64) self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc) self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)