diff --git a/bench/arty.py b/bench/arty.py index 94389ed..b8e720a 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -42,7 +42,7 @@ class BenchSoC(SoCCore): pads = self.platform.request("eth"), with_hw_init_reset = False) self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy, buffer_depth=256) + self.add_etherbone(phy=self.ethphy, buffer_depth=128) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) diff --git a/bench/colorlight_5a_75b.py b/bench/colorlight_5a_75b.py index a7e0d86..1a1a3dd 100755 --- a/bench/colorlight_5a_75b.py +++ b/bench/colorlight_5a_75b.py @@ -43,7 +43,7 @@ class BenchSoC(SoCCore): tx_delay = 0e-9, with_hw_init_reset = False) self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy, buffer_depth=256) + self.add_etherbone(phy=self.ethphy, buffer_depth=128) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) diff --git a/bench/genesys2.py b/bench/genesys2.py index f5490ba..60cc805 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -42,7 +42,7 @@ class BenchSoC(SoCCore): pads = self.platform.request("eth"), with_hw_init_reset = False) self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy, buffer_depth=256) + self.add_etherbone(phy=self.ethphy, buffer_depth=128) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) diff --git a/bench/test_etherbone.py b/bench/test_etherbone.py index f7115fb..54185e0 100755 --- a/bench/test_etherbone.py +++ b/bench/test_etherbone.py @@ -105,7 +105,7 @@ def speed_test(port): wb.open() test_size = 16*KiB - burst_size = 255 # FIXME: Use 256, fix Etherbone encoding. + burst_size = 128 print("Testing write speed... ", end="") start = time.time()