uniformize litex cores
This commit is contained in:
Florent Kermarrec
parent
4e08d6e9f9
commit
c42aa09878
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@ -3,6 +3,9 @@ __pycache__/
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*.py[cod]
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*$py.class
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# C extensions
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*.so
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# Distribution / packaging
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.Python
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env/
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@ -42,18 +45,45 @@ coverage.xml
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*,cover
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.hypothesis/
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# Translations
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*.mo
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*.pot
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# Django stuff:
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*.log
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local_settings.py
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# Flask stuff:
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instance/
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.webassets-cache
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# Scrapy stuff:
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.scrapy
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# Sphinx documentation
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docs/_build/
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# PyBuilder
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target/
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# IPython Notebook
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.ipynb_checkpoints
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# pyenv
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.python-version
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# celery beat schedule file
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celerybeat-schedule
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# dotenv
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.env
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# virtualenv
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venv/
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ENV/
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# Spyder project settings
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.spyderproject
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# Rope project settings
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.ropeproject
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2
LICENSE
2
LICENSE
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@ -1,4 +1,4 @@
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Unless otherwise noted, LiteEth is copyright (C) 2015 Florent Kermarrec.
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Unless otherwise noted, LiteEth is Copyright 2012-2018 / EnjoyDigital
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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82
README
82
README
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@ -3,22 +3,18 @@
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/ /__/ / __/ -_) _// __/ _ \
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/____/_/\__/\__/___/\__/_//_/
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Copyright 2012-2017 / EnjoyDigital
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Copyright 2012-2018 / EnjoyDigital
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A small footprint and configurable Ethernet core
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with UDP/IP hw stack and Etherbone frontend
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powered by LiteX
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powered by LiteX & Migen
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[> Intro
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---------
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--------
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LiteEth provides a small footprint and configurable Ethernet core.
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LiteEth is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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@ -32,10 +28,19 @@ LiteEth can be used as LiteX library or can be integrated with your standard
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design flow by generating the verilog rtl that you will use as a standard core.
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[> Features
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------------
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- Ethernet MAC with various interfaces and various PHYs (GMII, MII, RGMII, etc)
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- Hardware UDP/IP stack with ARP and ICMP
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- lwIP and uIP TCP/IP stacks ported and tested on lm32 and mor1kx
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-----------
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PHY:
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- MII / RMII
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- GMII / RGMII
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Core:
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- MAC with various interfaces (to soft core or hardware stack)
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- ARP
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- ICMP
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- UDP
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Frontend:
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- Etherbone (Wishbone over UDP, Slave or Master support)
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- Virtual Serial ports over UDP.
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[> FPGA Proven
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---------------
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@ -46,61 +51,39 @@ LiteEth is already used in commercial and open-source designs:
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- and others commercial designs...
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[> Possible improvements
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-------------------------
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------------------------
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- optimize ressources on HW ICMP and Etherbone (parameters buffering)
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- add standardized interfaces (AXI, Avalon-ST)
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- add DMA interface to MAC
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- add RGMII/SGMII PHYs
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- add SGMII PHYs
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- add more documentation
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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devel [AT] lists.m-labs.hk.
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enjoy-digital.fr.
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[> Getting started
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-------------------
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------------------
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1. Install Python3 and your vendor's software
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2. Obtain LiteX and install it:
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git clone https://github.com/enjoy-digital/litex --recursive
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cd litex
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python3 setup.py install
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python3 setup.py develop
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cd ..
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3. Build and load UDP loopback design (only for KC705 for now):
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go to example_designs/
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run ./make.py -t udp all load-bitstream
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4. Test design (only for KC705 for now):
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try to ping 192.168.1.50
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go to example_designs/test/
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run ./test_udp.py
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5. Build and load Etherbone design (only for KC705 for now):
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python3 make.py -t etherbone all load-bitstream
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6. Test design (only for KC705 for now):
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try to ping 192.168.1.50
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go to example_designs/test/
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run ./test_etherbone.py
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[> Simulations
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---------------
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Unit tests are available in ./test/.
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To run all the unit tests:
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./setup.py test
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Tests can also be run individually:
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python3 -m unittest test.test_name
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3. TODO: add/describe example design(s)
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[> Tests
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---------
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An Etherbone example with Wishbone SRAM and an UDP loopback example are provided.
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Please goto to Getting Started section to see how to run the tests.
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--------
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Unit tests are available in ./test/.
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To run all the unit tests:
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./setup.py test
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Tests can also be run individually:
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python3 -m unittest test.test_name
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[> License
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-----------
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----------
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LiteEth is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteEth for closed-source
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proprietary designs.
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@ -113,10 +96,10 @@ do them if possible:
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- send us the modifications and improvements you have done to LiteEth.
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[> Support and consulting
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--------------------------
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-------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteEth is mainly developed and maintained by EnjoyDigital.
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LiteEth is developed and maintained by EnjoyDigital.
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If you would like to know more about LiteEth or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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@ -126,4 +109,5 @@ So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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----------
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E-mail: florent [AT] enjoy-digital.fr
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6
setup.py
6
setup.py
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@ -5,14 +5,14 @@ from setuptools import setup
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from setuptools import find_packages
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if sys.version_info[:3] < (3, 3):
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raise SystemExit("You need Python 3.3+")
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if sys.version_info[:3] < (3, 5):
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raise SystemExit("You need Python 3.5+")
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setup(
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name="liteeth",
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version="0.1",
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description="small footprint and configurable Ethernet core",
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description="Small footprint and configurable Ethernet core",
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long_description=open("README").read(),
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author="Florent Kermarrec",
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author_email="florent@enjoy-digital.fr",
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