diff --git a/.gitignore b/.gitignore index 18bd967..72364f9 100644 --- a/.gitignore +++ b/.gitignore @@ -3,6 +3,9 @@ __pycache__/ *.py[cod] *$py.class +# C extensions +*.so + # Distribution / packaging .Python env/ @@ -42,18 +45,45 @@ coverage.xml *,cover .hypothesis/ +# Translations +*.mo +*.pot + +# Django stuff: +*.log +local_settings.py + +# Flask stuff: +instance/ +.webassets-cache + +# Scrapy stuff: +.scrapy + # Sphinx documentation docs/_build/ # PyBuilder target/ +# IPython Notebook +.ipynb_checkpoints + # pyenv .python-version +# celery beat schedule file +celerybeat-schedule + # dotenv .env # virtualenv venv/ ENV/ + +# Spyder project settings +.spyderproject + +# Rope project settings +.ropeproject diff --git a/LICENSE b/LICENSE index cbbfe8b..09cf76e 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Unless otherwise noted, LiteEth is copyright (C) 2015 Florent Kermarrec. +Unless otherwise noted, LiteEth is Copyright 2012-2018 / EnjoyDigital Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/README b/README index 517009e..ab2a95f 100644 --- a/README +++ b/README @@ -3,22 +3,18 @@ / /__/ / __/ -_) _// __/ _ \ /____/_/\__/\__/___/\__/_//_/ - Copyright 2012-2017 / EnjoyDigital + Copyright 2012-2018 / EnjoyDigital A small footprint and configurable Ethernet core - with UDP/IP hw stack and Etherbone frontend - powered by LiteX + powered by LiteX & Migen [> Intro ---------- +-------- LiteEth provides a small footprint and configurable Ethernet core. LiteEth is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations -ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... - -The core uses simple and specific streaming buses and will provides in the future -adapters to use standardized AXI or Avalon-ST streaming buses. +of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... Since Python is used to describe the HDL, the core is highly and easily configurable. @@ -32,10 +28,19 @@ LiteEth can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core. [> Features ------------- -- Ethernet MAC with various interfaces and various PHYs (GMII, MII, RGMII, etc) -- Hardware UDP/IP stack with ARP and ICMP -- lwIP and uIP TCP/IP stacks ported and tested on lm32 and mor1kx +----------- +PHY: + - MII / RMII + - GMII / RGMII +Core: + - MAC with various interfaces (to soft core or hardware stack) + - ARP + - ICMP + - UDP +Frontend: + - Etherbone (Wishbone over UDP, Slave or Master support) + - Virtual Serial ports over UDP. + [> FPGA Proven --------------- @@ -46,61 +51,39 @@ LiteEth is already used in commercial and open-source designs: - and others commercial designs... [> Possible improvements -------------------------- +------------------------ - optimize ressources on HW ICMP and Etherbone (parameters buffering) - add standardized interfaces (AXI, Avalon-ST) - add DMA interface to MAC -- add RGMII/SGMII PHYs +- add SGMII PHYs - add more documentation - ... See below Support and consulting :) If you want to support these features, please contact us at florent [AT] -enjoy-digital.fr. You can also contact our partner on the public mailing list -devel [AT] lists.m-labs.hk. - +enjoy-digital.fr. [> Getting started -------------------- +------------------ 1. Install Python3 and your vendor's software 2. Obtain LiteX and install it: git clone https://github.com/enjoy-digital/litex --recursive cd litex - python3 setup.py install + python3 setup.py develop cd .. -3. Build and load UDP loopback design (only for KC705 for now): - go to example_designs/ - run ./make.py -t udp all load-bitstream - -4. Test design (only for KC705 for now): - try to ping 192.168.1.50 - go to example_designs/test/ - run ./test_udp.py - -5. Build and load Etherbone design (only for KC705 for now): - python3 make.py -t etherbone all load-bitstream - -6. Test design (only for KC705 for now): - try to ping 192.168.1.50 - go to example_designs/test/ - run ./test_etherbone.py - -[> Simulations ---------------- - Unit tests are available in ./test/. - To run all the unit tests: - ./setup.py test - Tests can also be run individually: - python3 -m unittest test.test_name +3. TODO: add/describe example design(s) [> Tests ---------- - An Etherbone example with Wishbone SRAM and an UDP loopback example are provided. - Please goto to Getting Started section to see how to run the tests. +-------- +Unit tests are available in ./test/. +To run all the unit tests: + ./setup.py test +Tests can also be run individually: + python3 -m unittest test.test_name [> License ------------ +---------- LiteEth is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteEth for closed-source proprietary designs. @@ -113,10 +96,10 @@ do them if possible: - send us the modifications and improvements you have done to LiteEth. [> Support and consulting --------------------------- +------------------------- We love open-source hardware and like sharing our designs with others. -LiteEth is mainly developed and maintained by EnjoyDigital. +LiteEth is developed and maintained by EnjoyDigital. If you would like to know more about LiteEth or if you are already a happy user and would like to extend it for your needs, EnjoyDigital can provide standard @@ -126,4 +109,5 @@ So feel free to contact us, we'd love to work with you! (and eventually shorten the list of the possible improvements :) [> Contact +---------- E-mail: florent [AT] enjoy-digital.fr \ No newline at end of file diff --git a/setup.py b/setup.py index 413f806..7998352 100755 --- a/setup.py +++ b/setup.py @@ -5,14 +5,14 @@ from setuptools import setup from setuptools import find_packages -if sys.version_info[:3] < (3, 3): - raise SystemExit("You need Python 3.3+") +if sys.version_info[:3] < (3, 5): + raise SystemExit("You need Python 3.5+") setup( name="liteeth", version="0.1", - description="small footprint and configurable Ethernet core", + description="Small footprint and configurable Ethernet core", long_description=open("README").read(), author="Florent Kermarrec", author_email="florent@enjoy-digital.fr",