From c6875b7bff2cb0c04283d2ed02cd6cdd198080e1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 31 Mar 2016 21:27:08 +0200 Subject: [PATCH] example_designs: use new litescope --- example_designs/targets/base.py | 14 ++++++-------- example_designs/targets/etherbone.py | 14 ++++++-------- example_designs/targets/tty.py | 14 ++++++-------- example_designs/targets/udp.py | 14 ++++++-------- 4 files changed, 24 insertions(+), 32 deletions(-) diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index bd1a8a0..3b66e10 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -60,12 +60,11 @@ set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] class BaseSoCDevel(BaseSoC): csr_map = { - "logic_analyzer": 20 + "analyzer": 20 } csr_map.update(BaseSoC.csr_map) def __init__(self, platform): - from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer - from litescope.core.port import LiteScopeTerm + from litescope import LiteScopeAnalyzer BaseSoC.__init__(self, platform) self.core_icmp_rx_fsm_state = Signal(4) @@ -78,7 +77,7 @@ class BaseSoCDevel(BaseSoC): self.core_arp_tx_fsm_state = Signal(4) self.core_arp_table_fsm_state = Signal(4) - debug = ( + debug = [ # MAC interface self.core.mac.core.sink.valid, self.core.mac.core.sink.last, @@ -122,9 +121,8 @@ class BaseSoCDevel(BaseSoC): self.core_udp_rx_fsm_state, self.core_udp_tx_fsm_state - ) - self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) - self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) + ] + self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) def do_finalize(self): BaseSoC.do_finalize(self) @@ -144,6 +142,6 @@ class BaseSoCDevel(BaseSoC): ] def do_exit(self, vns): - self.logic_analyzer.export(vns, "test/logic_analyzer.csv") + self.analyzer.export_csv(vns, "test/analyzer.csv") default_subtarget = BaseSoC diff --git a/example_designs/targets/etherbone.py b/example_designs/targets/etherbone.py index 8e8acd6..3e4dcab 100644 --- a/example_designs/targets/etherbone.py +++ b/example_designs/targets/etherbone.py @@ -16,14 +16,13 @@ class EtherboneSoC(BaseSoC): class EtherboneSoCDevel(EtherboneSoC): csr_map = { - "logic_analyzer": 20 + "analyzer": 20 } csr_map.update(EtherboneSoC.csr_map) def __init__(self, platform): - from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer - from litescope.core.port import LiteScopeTerm + from litescope import LiteScopeAnalyzer EtherboneSoC.__init__(self, platform) - debug = ( + debug = [ # mmap stream from HOST self.etherbone.master.sink.valid, self.etherbone.master.sink.last, @@ -58,11 +57,10 @@ class EtherboneSoCDevel(EtherboneSoC): self.etherbone.master.bus.cti, self.etherbone.master.bus.bte, self.etherbone.master.bus.err - ) - self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) - self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) + ] + self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) def do_exit(self, vns): - self.logic_analyzer.export(vns, "test/logic_analyzer.csv") + self.analyzer.export_csv(vns, "test/analyzer.csv") default_subtarget = EtherboneSoC diff --git a/example_designs/targets/tty.py b/example_designs/targets/tty.py index f5ad5bc..2d2ce4b 100644 --- a/example_designs/targets/tty.py +++ b/example_designs/targets/tty.py @@ -16,14 +16,13 @@ class TTYSoC(BaseSoC): class TTYSoCDevel(TTYSoC): csr_map = { - "logic_analyzer": 20 + "analyzer": 20 } csr_map.update(TTYSoC.csr_map) def __init__(self, platform): - from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer - from litescope.core.port import LiteScopeTerm + from litescope import LiteScopeAnalyzer TTYSoC.__init__(self, platform) - debug = ( + debug = [ self.tty.sink.valid, self.tty.sink.ready, self.tty.sink.data, @@ -31,11 +30,10 @@ class TTYSoCDevel(TTYSoC): self.tty.source.valid, self.tty.source.ready, self.tty.source.data - ) - self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) - self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) + ] + self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) def do_exit(self, vns): - self.logic_analyzer.export(vns, "test/logic_analyzer.csv") + self.analyzer.export_csv(vns, "test/analyzer.csv") default_subtarget = TTYSoC diff --git a/example_designs/targets/udp.py b/example_designs/targets/udp.py index 17a7e54..1f1c6e2 100644 --- a/example_designs/targets/udp.py +++ b/example_designs/targets/udp.py @@ -27,14 +27,13 @@ class UDPSoC(BaseSoC): class UDPSoCDevel(UDPSoC): csr_map = { - "logic_analyzer": 20 + "analyzer": 20 } csr_map.update(UDPSoC.csr_map) def __init__(self, platform): - from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer - from litescope.core.port import LiteScopeTerm + from litescope import LiteScopeAnalyzer UDPSoC.__init__(self, platform) - debug = ( + debug = [ self.loopback_8.sink.valid, self.loopback_8.sink.last, self.loopback_8.sink.ready, @@ -54,11 +53,10 @@ class UDPSoCDevel(UDPSoC): self.loopback_32.source.last, self.loopback_32.source.ready, self.loopback_32.source.data - ) - self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096) - self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) + ] + self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) def do_exit(self, vns): - self.logic_analyzer.export(vns, "test/logic_analyzer.csv") + self.analyzer.export_csv(vns, "test/analyzer.csv") default_subtarget = UDPSoC