diff --git a/bench/arty.py b/bench/arty.py
index 0574e43..97f5021 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -28,7 +28,10 @@ class BenchSoC(SoCCore):
         platform = arty.Platform()
 
         # SoCMini ----------------------------------------------------------------------------------
-        SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, uart_name="bridge")
+        SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident          = "LiteEth bench on Arty",
+            ident_version  = True
+        )
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -41,6 +44,9 @@ class BenchSoC(SoCCore):
         self.add_csr("ethphy")
         self.add_etherbone(phy=self.ethphy)
 
+        # SRAM -------------------------------------------------------------------------------------
+        self.add_ram("sram", 0x20000000, 0x1000)
+
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser
         self.submodules.leds = LedChaser(
diff --git a/bench/genesys2.py b/bench/genesys2.py
index 0a07199..3e9a7ca 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -28,7 +28,10 @@ class BenchSoC(SoCCore):
         platform = genesys2.Platform()
 
         # SoCMini ----------------------------------------------------------------------------------
-        SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, uart_name="bridge")
+        SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident          = "LiteEth bench on Genesys2",
+            ident_version  = True
+        )
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -41,6 +44,9 @@ class BenchSoC(SoCCore):
         self.add_csr("ethphy")
         self.add_etherbone(phy=self.ethphy)
 
+        # SRAM -------------------------------------------------------------------------------------
+        self.add_ram("sram", 0x20000000, 0x1000)
+
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser
         self.submodules.leds = LedChaser(