bench/targets: add identifier and SRAM.
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@ -28,7 +28,10 @@ class BenchSoC(SoCCore):
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platform = arty.Platform()
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, uart_name="bridge")
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteEth bench on Arty",
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ident_version = True
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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@ -41,6 +44,9 @@ class BenchSoC(SoCCore):
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy)
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# SRAM -------------------------------------------------------------------------------------
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self.add_ram("sram", 0x20000000, 0x1000)
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.submodules.leds = LedChaser(
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@ -28,7 +28,10 @@ class BenchSoC(SoCCore):
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platform = genesys2.Platform()
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, uart_name="bridge")
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteEth bench on Genesys2",
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ident_version = True
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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@ -41,6 +44,9 @@ class BenchSoC(SoCCore):
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy)
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# SRAM -------------------------------------------------------------------------------------
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self.add_ram("sram", 0x20000000, 0x1000)
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.submodules.leds = LedChaser(
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