From ca4284f97764093902475e8cdb9c407ee402b71b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 24 Nov 2020 10:19:23 +0100
Subject: [PATCH] bench: add colorlight_5a_75b test target.

---
 bench/colorlight_5a_75b.py | 75 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100755 bench/colorlight_5a_75b.py

diff --git a/bench/colorlight_5a_75b.py b/bench/colorlight_5a_75b.py
new file mode 100755
index 0000000..5c32431
--- /dev/null
+++ b/bench/colorlight_5a_75b.py
@@ -0,0 +1,75 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteEth.
+#
+# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import argparse
+
+from migen import *
+
+from litex_boards.platforms import colorlight_5a_75b
+from litex_boards.targets.colorlight_5a_75x import _CRG
+
+from litex.soc.cores.clock import *
+from litex.soc.interconnect.csr import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
+
+# Bench SoC ----------------------------------------------------------------------------------------
+
+class BenchSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(50e6)):
+        platform = colorlight_5a_75b.Platform()
+
+        # SoCMini ----------------------------------------------------------------------------------
+        SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident          = "LiteEth bench on ColorLight 5A-75B",
+            ident_version  = True
+        )
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # Etherbone --------------------------------------------------------------------------------
+        self.submodules.ethphy = LiteEthPHYRGMII(
+            clock_pads = self.platform.request("eth_clocks"),
+            pads       = self.platform.request("eth"),
+            tx_delay   = 0e-9,
+            with_hw_init_reset = False)
+        self.add_csr("ethphy")
+        self.add_etherbone(phy=self.ethphy)
+
+        # SRAM -------------------------------------------------------------------------------------
+        self.add_ram("sram", 0x20000000, 0x1000)
+
+        # Leds -------------------------------------------------------------------------------------
+        from litex.soc.cores.led import LedChaser
+        self.submodules.leds = LedChaser(
+            pads         = platform.request_all("user_led_n"),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
+# Main ---------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteEth Bench on ColorLight 5A-75B")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    args = parser.parse_args()
+
+    soc     = BenchSoC()
+    builder = Builder(soc, csr_csv="csr.csv")
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
+
+if __name__ == "__main__":
+    main()