From ca9cbd15559aee15bb11e048e55d6e3dd4c3e846 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 12 Feb 2020 15:09:57 +0100 Subject: [PATCH] Move more options to config file --- examples/udp_s7phyrgmii.yml | 18 +++++++++--------- examples/wishbone_mii.yml | 15 +++++++-------- liteeth/gen.py | 24 +++++++++++------------- 3 files changed, 27 insertions(+), 30 deletions(-) diff --git a/examples/udp_s7phyrgmii.yml b/examples/udp_s7phyrgmii.yml index f3bd033..7b7c962 100644 --- a/examples/udp_s7phyrgmii.yml +++ b/examples/udp_s7phyrgmii.yml @@ -1,12 +1,12 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD -{ - # PHY ---------------------------------------------------------------------- - "phy": "LiteEthS7PHYRGMII", - "vendor": "xilinx", - # Core --------------------------------------------------------------------- - "core": "udp", - "mac_address": 0x10e2d5000000, - "ip_address": "192.168.1.50", -} +# PHY ---------------------------------------------------------------------- +phy: LiteEthS7PHYRGMII +vendor: xilinx +# Core --------------------------------------------------------------------- +clk_freq: 100e6 +core: udp +mac_address: 0x10e2d5000000 +ip_address: 192.168.1.50 +port: 6000 diff --git a/examples/wishbone_mii.yml b/examples/wishbone_mii.yml index c10b8e8..a423df5 100644 --- a/examples/wishbone_mii.yml +++ b/examples/wishbone_mii.yml @@ -1,11 +1,10 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD -{ - # PHY ---------------------------------------------------------------------- - "phy": "LiteEthPHYMII", - "vendor": "xilinx", - # Core --------------------------------------------------------------------- - "core": "wishbone", - "endianness": "big", -} +# PHY ---------------------------------------------------------------------- +phy: LiteEthPHYMII +vendor: xilinx +# Core --------------------------------------------------------------------- +clk_freq: 100e6 +core: wishbone +endianness: big diff --git a/liteeth/gen.py b/liteeth/gen.py index 126e4a9..00d45fd 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -203,10 +203,10 @@ class MACCore(PHYCore): "ethmac": 0x50000000 }) - def __init__(self, phy, clk_freq, platform, endianness): - PHYCore.__init__(self, phy, clk_freq, platform) + def __init__(self, platform, core_config): + PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=endianness) + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"]) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") @@ -225,11 +225,11 @@ class MACCore(PHYCore): # UDP Core ----------------------------------------------------------------------------------------- class UDPCore(PHYCore): - def __init__(self, phy, clk_freq, mac_address, ip_address, port, platform): - PHYCore.__init__(self, phy, clk_freq, platform) + def __init__(self, platform, core_config): + PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform) - self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq) - udp_port = self.core.udp.crossbar.get_port(port, 8) + self.submodules.core = LiteEthUDPIPCore(self.ethphy, core_config["mac_address"], convert_ip(core_config["ip_address"]), core_config["clk_freq"]) + udp_port = self.core.udp.crossbar.get_port(core_config["port"], 8) # XXX avoid manual connect udp_sink = self.platform.request("udp_sink") self.comb += [ @@ -284,6 +284,8 @@ def main(): core_config[k] = replaces[r] if k == "phy": core_config[k] = getattr(liteeth_phys, core_config[k]) + if k == "clk_freq": + core_config[k] = int(float(core_config[k])) # Generate core -------------------------------------------------------------------------------- if core_config["vendor"] == "lattice": @@ -295,13 +297,9 @@ def main(): platform.add_extension(_io) if core_config["core"] == "wishbone": - soc = MACCore(phy=core_config["phy"], clk_freq=int(100e6), platform=platform, endianness=core_config["endianness"]) + soc = MACCore(platform, core_config) elif core_config["core"] == "udp": - soc = UDPCore(phy=core_config["phy"], clk_freq=int(100e6), - mac_address = core_config["mac_address"], - ip_address = core_config["ip_address"], - port = 6000, - platform = platform) + soc = UDPCore(platform, core_config) else: raise ValueError("Unknown core: {}".format(core_config["core"]))