From cb1e1932b3db621472738919c358e94076be2db4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 1 Aug 2023 14:42:16 +0200 Subject: [PATCH] global: Use new WaitTimer integrated cast to int. --- bench/arty.py | 2 +- liteeth/core/dhcp.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index ad04278..9b52d30 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -95,7 +95,7 @@ class BenchSoC(SoCCore): self.specials += MultiReg(switches_pads, switches) # Send Switches value on UDP Streamer TX every 500ms. - switches_timer = WaitTimer(int(500e-3*sys_clk_freq)) + switches_timer = WaitTimer(500e-3*sys_clk_freq) switches_fsm = FSM(reset_state="IDLE") self.submodules += switches_timer, switches_fsm switches_fsm.act("IDLE", diff --git a/liteeth/core/dhcp.py b/liteeth/core/dhcp.py index 0cf4963..4dd5167 100644 --- a/liteeth/core/dhcp.py +++ b/liteeth/core/dhcp.py @@ -575,7 +575,7 @@ class LiteEthDHCP(LiteXModule): ] # DHCP Timeout. - self.timeout_timer = timeout_timer = WaitTimer(int(timeout*sys_clk_freq)) + self.timeout_timer = timeout_timer = WaitTimer(timeout*sys_clk_freq) self.comb += [ timeout_timer.wait.eq(~self.done), self.timeout.eq(timeout_timer.done),