From cd413c5c20215225b002e46862a283a87814d7c5 Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Mon, 27 Jan 2020 10:32:38 -0800 Subject: [PATCH] phy/usrgmii.py: IDELAYE3 requires EN_VTC to be enabled for fixed mode time delay. This eliminates implementation time CRITICAL WARNINGs and ensures generating a bitfile. --- liteeth/phy/usrgmii.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py index c7e8d01..61d4099 100644 --- a/liteeth/phy/usrgmii.py +++ b/liteeth/phy/usrgmii.py @@ -77,7 +77,7 @@ class LiteEthPHYRGMIIRX(Module): i_CNTVALUEIN=0, i_IDATAIN=rx_ctl_ibuf, i_RST=0, - i_EN_VTC=0, + i_EN_VTC=1, o_DATAOUT=rx_ctl_idelay), Instance("IDDRE1", p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", @@ -110,7 +110,7 @@ class LiteEthPHYRGMIIRX(Module): i_CNTVALUEIN=0, i_IDATAIN=rx_data_ibuf[i], i_RST=0, - i_EN_VTC=0, + i_EN_VTC=1, o_DATAOUT=rx_data_idelay[i]), Instance("IDDRE1", p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",