diff --git a/liteeth/core/mac/__init__.py b/liteeth/core/mac/__init__.py
index 59e30e3..cac1765 100644
--- a/liteeth/core/mac/__init__.py
+++ b/liteeth/core/mac/__init__.py
@@ -27,7 +27,7 @@ class LiteEthMAC(Module, AutoCSR):
             self.rx_slots = CSRConstant(nrxslots)
             self.tx_slots = CSRConstant(ntxslots)
             self.slot_size = CSRConstant(2**bits_for(eth_mtu))
-            self.submodules.interface = LiteEthMACWishboneInterface(dw, nrxslots, ntxslots)
+            self.submodules.interface = LiteEthMACWishboneInterface(dw, nrxslots, ntxslots, endianness)
             self.comb += Port.connect(self.interface, self.core)
             self.ev, self.bus = self.interface.sram.ev, self.interface.bus
             self.csrs = self.interface.get_csrs() + self.core.get_csrs()
diff --git a/liteeth/core/mac/sram.py b/liteeth/core/mac/sram.py
index fc9fd1f..ba31692 100644
--- a/liteeth/core/mac/sram.py
+++ b/liteeth/core/mac/sram.py
@@ -5,7 +5,7 @@ from litex.soc.interconnect.csr_eventmanager import *
 
 
 class LiteEthMACSRAMWriter(Module, AutoCSR):
-    def __init__(self, dw, depth, nslots=2):
+    def __init__(self, dw, depth, nslots=2, endianness="big"):
         self.sink = sink = stream.Endpoint(eth_phy_description(dw))
         self.crc_error = Signal()
 
@@ -27,17 +27,19 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
         sink.ready.reset = 1
 
         # length computation
-        increment = Signal(3)
-        self.comb += \
-            If(sink.last_be[3],
-                increment.eq(1)
-            ).Elif(sink.last_be[2],
-                increment.eq(2)
-            ).Elif(sink.last_be[1],
-                increment.eq(3)
-            ).Else(
-                increment.eq(4)
-            )
+        inc = Signal(3)
+        inc_cases = {}
+        inc_cases["default"] = inc.eq(4)
+        if endianness == "big":
+            inc_cases[0b1000] = inc.eq(1)
+            inc_cases[0b0100] = inc.eq(2)
+            inc_cases[0b0010] = inc.eq(3)
+        else:
+            inc_cases[0b0001] = inc.eq(1)
+            inc_cases[0b0010] = inc.eq(2)
+            inc_cases[0b0100] = inc.eq(3)
+        self.comb += Case(sink.last_be, inc_cases)
+
         counter = Signal(lengthbits)
         counter_reset = Signal()
         counter_ce = Signal()
@@ -45,7 +47,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
             If(counter_reset,
                 counter.eq(0)
             ).Elif(counter_ce,
-                counter.eq(counter + increment)
+                counter.eq(counter + inc)
             )
 
         # slot computation
@@ -140,7 +142,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
 
 
 class LiteEthMACSRAMReader(Module, AutoCSR):
-    def __init__(self, dw, depth, nslots=2):
+    def __init__(self, dw, depth, nslots=2, endianness="big"):
         self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         slotbits = max(log2_int(nslots), 1)
@@ -202,20 +204,21 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
                 NextState("END"),
             )
         )
+
         length_lsb = fifo.source.length[0:2]
-        self.comb += [
-            If(last,
-                If(length_lsb == 3,
-                    source.last_be.eq(0b0010)
-                ).Elif(length_lsb == 2,
-                    source.last_be.eq(0b0100)
-                ).Elif(length_lsb == 1,
-                    source.last_be.eq(0b1000)
-                ).Else(
-                    source.last_be.eq(0b0001)
-                )
-            )
-        ]
+        length_cases = {}
+        if endianness == "big":
+            length_cases[0] = source.last_be.eq(0b0001)
+            length_cases[1] = source.last_be.eq(0b1000)
+            length_cases[2] = source.last_be.eq(0b0100)
+            length_cases[3] = source.last_be.eq(0b0010)
+        else:
+            length_cases[0] = source.last_be.eq(0b1000)
+            length_cases[1] = source.last_be.eq(0b0001)
+            length_cases[2] = source.last_be.eq(0b0010)
+            length_cases[3] = source.last_be.eq(0b0100)
+        self.comb += If(last, Case(length_lsb, length_cases))
+
         fsm.act("SEND",
             source.valid.eq(1),
             source.last.eq(last),
@@ -253,8 +256,8 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
 
 
 class LiteEthMACSRAM(Module, AutoCSR):
-    def __init__(self, dw, depth, nrxslots, ntxslots):
-        self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots)
-        self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots)
+    def __init__(self, dw, depth, nrxslots, ntxslots, endianness):
+        self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots, endianness)
+        self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots, endianness)
         self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
         self.sink, self.source = self.writer.sink, self.reader.source
diff --git a/liteeth/core/mac/wishbone.py b/liteeth/core/mac/wishbone.py
index 1aebfc8..d920db4 100644
--- a/liteeth/core/mac/wishbone.py
+++ b/liteeth/core/mac/wishbone.py
@@ -7,7 +7,7 @@ from litex.soc.interconnect import wishbone
 
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):
-    def __init__(self, dw, nrxslots=2, ntxslots=2):
+    def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big"):
         self.sink = stream.Endpoint(eth_phy_description(dw))
         self.source = stream.Endpoint(eth_phy_description(dw))
         self.bus = wishbone.Interface()
@@ -16,7 +16,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
 
         # storage in SRAM
         sram_depth = eth_mtu//(dw//8)
-        self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
+        self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness)
         self.comb += [
             self.sink.connect(self.sram.sink),
             self.sram.source.connect(self.source)