diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index c9f6491..8b2daed 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -21,13 +21,13 @@ class LiteEthMAC(Module, AutoCSR):
         hw_mac            = None,
         timestamp         = None,
         full_memory_we    = False,
-        sys_data_path     = False):
+        with_sys_datapath = False):
 
         assert dw%8 == 0
         assert interface  in ["crossbar", "wishbone", "hybrid"]
         assert endianness in ["big", "little"]
 
-        self.submodules.core = LiteEthMACCore(phy, dw, with_preamble_crc, sys_data_path)
+        self.submodules.core = LiteEthMACCore(phy, dw, with_preamble_crc, with_sys_datapath)
         self.csrs = []
         if interface == "crossbar":
             self.submodules.crossbar     = LiteEthMACCrossbar(dw)
diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py
index 2677396..0a8f2bb 100644
--- a/liteeth/mac/core.py
+++ b/liteeth/mac/core.py
@@ -19,8 +19,8 @@ from litex.soc.interconnect.stream import BufferizeEndpoints, DIR_SOURCE, DIR_SI
 
 class LiteEthMACCore(Module, AutoCSR):
     def __init__(self, phy, dw,
+                 with_sys_datapath = False,
                  with_preamble_crc = True,
-                 sys_data_path     = True,
                  with_padding      = True):
         core_dw = dw
 
@@ -30,7 +30,7 @@ class LiteEthMACCore(Module, AutoCSR):
         rx_pipeline = [phy]
         tx_pipeline = [phy]
 
-        if sys_data_path:
+        if with_sys_datapath:
             self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw)
             cd_tx = cd_rx = "sys"
             dw = core_dw
@@ -93,7 +93,7 @@ class LiteEthMACCore(Module, AutoCSR):
             tx_pipeline += [padding_inserter]
             rx_pipeline += [padding_checker]
 
-        if not sys_data_path:
+        if not with_sys_datapath:
             self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw)
 
         # Graph