From cfe320185451e99913f35df06d166a9baad631a9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 13 Jun 2023 17:30:20 +0200 Subject: [PATCH] phy/usp_gty_1000basex: Working :), remove debug. --- bench/xcu1525.py | 13 ------------- liteeth/phy/usp_gty_1000basex.py | 17 ----------------- 2 files changed, 30 deletions(-) diff --git a/bench/xcu1525.py b/bench/xcu1525.py index 2aa69bc..50ac367 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -64,9 +64,6 @@ class BenchSoC(SoCCore): ident_version = True ) - # UARTBone --------------------------------------------------------------------------------- - self.add_uartbone() - # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq) @@ -86,16 +83,6 @@ class BenchSoC(SoCCore): sys_clk_freq = sys_clk_freq ) - # Litescope -------------------------------------------------------------------------------- - from litescope import LiteScopeAnalyzer - analyzer_signals = self.ethphy.debug - self.analyzer = LiteScopeAnalyzer(analyzer_signals, - depth = 256, - clock_domain = "sys", - csr_csv = "analyzer.csv" - ) - - # Main --------------------------------------------------------------------------------------------- def main(): diff --git a/liteeth/phy/usp_gty_1000basex.py b/liteeth/phy/usp_gty_1000basex.py index 0418b70..12a1829 100644 --- a/liteeth/phy/usp_gty_1000basex.py +++ b/liteeth/phy/usp_gty_1000basex.py @@ -5,8 +5,6 @@ # Copyright (c) 2018 Sebastien Bourdeauducq # SPDX-License-Identifier: BSD-2-Clause -# Work-In-Progress... - from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.cdc import PulseSynchronizer @@ -958,18 +956,3 @@ class USP_GTY_1000BASEX(LiteXModule): gearbox.tx_data.eq(pcs.tbi_tx), pcs.tbi_rx.eq(gearbox.rx_data) ] - - self.debug = [ - gtpowergood, - pll_reset, - pll_locked, - tx_reset, - tx_data, - tx_reset_done, - rx_reset, - rx_data, - rx_reset_done, - self.sink, - self.source, - self.link_up - ]