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liteeth_gen: Switch to LiteXModule and remove old TODO.

This commit is contained in:
Florent Kermarrec 2023-07-03 19:15:12 +02:00
parent f8594ae429
commit d29d90cd78
1 changed files with 8 additions and 7 deletions
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15
liteeth/gen.py
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@ -23,7 +23,6 @@ for some use cases it could be interesting to generate a standalone verilog file
The standalone core is generated from a YAML configuration file that allows the user to generate The standalone core is generated from a YAML configuration file that allows the user to generate
easily a custom configuration of the core. easily a custom configuration of the core.
TODO: identify limitations
""" """
import argparse import argparse
@ -32,6 +31,8 @@ import yaml
from migen import * from migen import *
from litex.gen import *
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform from litex.build.xilinx.platform import XilinxPlatform
from litex.build.lattice.platform import LatticePlatform from litex.build.lattice.platform import LatticePlatform
@ -205,7 +206,7 @@ class PHYCore(SoCMini):
SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args) SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset")) self.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset"))
# PHY -------------------------------------------------------------------------------------- # PHY --------------------------------------------------------------------------------------
phy = core_config["phy"] phy = core_config["phy"]
@ -263,7 +264,7 @@ class PHYCore(SoCMini):
self.comb += ethphy_pads.link_up.eq(ethphy.link_up) self.comb += ethphy_pads.link_up.eq(ethphy.link_up)
else: else:
raise ValueError("Unsupported PHY") raise ValueError("Unsupported PHY")
self.submodules.ethphy = ethphy self.ethphy = ethphy
# Timing constaints. # Timing constaints.
# Generate timing constraints to ensure the "keep" attribute is properly set on the various # Generate timing constraints to ensure the "keep" attribute is properly set on the various
@ -295,7 +296,7 @@ class MACCore(PHYCore):
PHYCore.__init__(self, platform, core_config) PHYCore.__init__(self, platform, core_config)
# MAC -------------------------------------------------------------------------------------- # MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = ethmac = LiteEthMAC( self.ethmac = ethmac = LiteEthMAC(
phy = self.ethphy, phy = self.ethphy,
dw = 32, dw = 32,
interface = "wishbone", interface = "wishbone",
@ -363,7 +364,7 @@ class UDPCore(PHYCore):
# Core ------------------------------------------------------------------------------------- # Core -------------------------------------------------------------------------------------
data_width = core_config.get("data_width", 8) data_width = core_config.get("data_width", 8)
self.submodules.core = LiteEthUDPIPCore(self.ethphy, self.core = LiteEthUDPIPCore(self.ethphy,
mac_address = mac_address, mac_address = mac_address,
ip_address = ip_address, ip_address = ip_address,
clk_freq = core_config["clk_freq"], clk_freq = core_config["clk_freq"],
@ -384,7 +385,7 @@ class UDPCore(PHYCore):
dhcp_mac_address = mac_address dhcp_mac_address = mac_address
else: else:
dhcp_mac_address = Signal(48, reset=0x10e2d5000001) dhcp_mac_address = Signal(48, reset=0x10e2d5000001)
self.submodules.dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=self.sys_clk_freq) self.dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=self.sys_clk_freq)
self.comb += [ self.comb += [
self.dhcp.start.eq(dhcp_pads.start), self.dhcp.start.eq(dhcp_pads.start),
dhcp_pads.done.eq(self.dhcp.done), dhcp_pads.done.eq(self.dhcp.done),
@ -400,7 +401,7 @@ class UDPCore(PHYCore):
if etherbone: if etherbone:
assert (data_width == 32) assert (data_width == 32)
self.submodules.etherbone = LiteEthEtherbone( self.etherbone = LiteEthEtherbone(
udp = self.core.udp, udp = self.core.udp,
udp_port = etherbone_port, udp_port = etherbone_port,
buffer_depth = etherbone_buffer_depth, buffer_depth = etherbone_buffer_depth,