From d38612db0c7bc0f26652ad0f86bc9bcc4e2fc202 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 27 Dec 2015 12:26:01 +0100 Subject: [PATCH] remove use of Record.connect --- example_designs/targets/tty.py | 2 +- liteeth/common.py | 6 ++---- liteeth/core/arp.py | 12 ++++++------ liteeth/core/icmp.py | 16 ++++++++-------- liteeth/core/ip.py | 12 ++++++------ liteeth/core/mac/__init__.py | 8 ++++---- liteeth/core/mac/core/crc.py | 4 ++-- liteeth/core/mac/core/gap.py | 2 +- liteeth/core/mac/core/padding.py | 4 ++-- liteeth/core/mac/core/preamble.py | 4 ++-- liteeth/core/mac/frontend/wishbone.py | 4 ++-- liteeth/core/udp.py | 20 ++++++++++---------- liteeth/frontend/etherbone.py | 26 +++++++++++++------------- liteeth/frontend/tty.py | 8 ++++---- liteeth/phy/gmii_mii.py | 12 ++++++------ liteeth/phy/mii.py | 2 +- liteeth/phy/rmii.py | 2 +- test/mac_core_tb.py | 8 ++++---- test/udp_tb.py | 4 ++-- 19 files changed, 77 insertions(+), 79 deletions(-) diff --git a/example_designs/targets/tty.py b/example_designs/targets/tty.py index 3e3713f..32dce9a 100644 --- a/example_designs/targets/tty.py +++ b/example_designs/targets/tty.py @@ -11,7 +11,7 @@ class TTYSoC(BaseSoC): mac_address=0x10e2d5000000, ip_address="192.168.0.42") self.submodules.tty = LiteEthTTY(self.core.udp, convert_ip("192.168.0.14"), 10000) - self.comb += Record.connect(self.tty.source, self.tty.sink) + self.comb += self.tty.source.connect(self.tty.sink) class TTYSoCDevel(TTYSoC): diff --git a/liteeth/common.py b/liteeth/common.py index ae02d87..f7a821e 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -18,10 +18,8 @@ def reverse_bytes(signal): class Port: def connect(self, port): - r = [ - Record.connect(self.source, port.sink), - Record.connect(port.source, self.sink) - ] + r = [self.source.connect(port.sink), + port.source.connect(self.sink)] return r diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py index 708a0fe..33644e3 100644 --- a/liteeth/core/arp.py +++ b/liteeth/core/arp.py @@ -71,7 +71,7 @@ class LiteEthARPTX(Module): ] fsm.act("SEND", packetizer.sink.stb.eq(1), - Record.connect(packetizer.source, source), + packetizer.source.connect(source), source.target_mac.eq(packetizer.sink.target_mac), source.sender_mac.eq(mac_address), source.ethernet_type.eq(ethernet_type_arp), @@ -102,7 +102,7 @@ class LiteEthARPRX(Module): # # # self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer() - self.comb += Record.connect(sink, depacketizer.sink) + self.comb += sink.connect(depacketizer.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -295,11 +295,11 @@ class LiteEthARP(Module): self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address) self.submodules.table = table = LiteEthARPTable(clk_freq) self.comb += [ - Record.connect(rx.source, table.sink), - Record.connect(table.source, tx.sink) + rx.source.connect(table.sink), + table.source.connect(tx.sink) ] mac_port = mac.crossbar.get_port(ethernet_type_arp) self.comb += [ - Record.connect(tx.source, mac_port.sink), - Record.connect(mac_port.source, rx.sink) + tx.source.connect(mac_port.sink), + mac_port.source.connect(rx.sink) ] diff --git a/liteeth/core/icmp.py b/liteeth/core/icmp.py index 34bfbdc..cb3f2d3 100644 --- a/liteeth/core/icmp.py +++ b/liteeth/core/icmp.py @@ -42,7 +42,7 @@ class LiteEthICMPTX(Module): ) ) fsm.act("SEND", - Record.connect(packetizer.source, source), + packetizer.source.connect(source), source.length.eq(sink.length + icmp_header.length), source.protocol.eq(icmp_protocol), source.ip_address.eq(sink.ip_address), @@ -69,7 +69,7 @@ class LiteEthICMPRX(Module): # # # self.submodules.depacketizer = depacketizer = LiteEthICMPDepacketizer() - self.comb += Record.connect(sink, depacketizer.sink) + self.comb += sink.connect(depacketizer.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -131,8 +131,8 @@ class LiteEthICMPEcho(Module): # TODO: optimize ressources (no need to store parameters as datas) self.submodules.buffer = Buffer(eth_icmp_user_description(8), 128, 2) self.comb += [ - Record.connect(sink, self.buffer.sink), - Record.connect(self.buffer.source, source), + sink.connect(self.buffer.sink), + self.buffer.source.connect(source), self.source.msgtype.eq(0x0), self.source.checksum.eq(~((~self.buffer.source.checksum)-0x0800)) ] @@ -145,11 +145,11 @@ class LiteEthICMP(Module): self.submodules.rx = rx = LiteEthICMPRX(ip_address) self.submodules.echo = echo = LiteEthICMPEcho() self.comb += [ - Record.connect(rx.source, echo.sink), - Record.connect(echo.source, tx.sink) + rx.source.connect(echo.sink), + echo.source.connect(tx.sink) ] ip_port = ip.crossbar.get_port(icmp_protocol) self.comb += [ - Record.connect(tx.source, ip_port.sink), - Record.connect(ip_port.source, rx.sink) + tx.source.connect(ip_port.sink), + ip_port.source.connect(rx.sink) ] diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 13ca436..dfeaf27 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -154,7 +154,7 @@ class LiteEthIPTX(Module): target_mac.eq(arp_table.response.mac_address) ) fsm.act("SEND", - Record.connect(packetizer.source, source), + packetizer.source.connect(source), source.ethernet_type.eq(ethernet_type_ip), source.target_mac.eq(target_mac), source.sender_mac.eq(mac_address), @@ -189,7 +189,7 @@ class LiteEthIPRX(Module): # # # self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer() - self.comb += Record.connect(sink, depacketizer.sink) + self.comb += sink.connect(depacketizer.sink) self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=False) self.comb += [ @@ -257,11 +257,11 @@ class LiteEthIP(Module): self.submodules.rx = rx = LiteEthIPRX(mac_address, ip_address) mac_port = mac.crossbar.get_port(ethernet_type_ip) self.comb += [ - Record.connect(tx.source, mac_port.sink), - Record.connect(mac_port.source, rx.sink) + tx.source.connect(mac_port.sink), + mac_port.source.connect(rx.sink) ] self.submodules.crossbar = crossbar = LiteEthIPV4Crossbar() self.comb += [ - Record.connect(crossbar.master.source, tx.sink), - Record.connect(rx.source, crossbar.master.sink) + crossbar.master.source.connect(tx.sink), + rx.source.connect(crossbar.master.sink) ] diff --git a/liteeth/core/mac/__init__.py b/liteeth/core/mac/__init__.py index dd1fb3f..b6d203b 100644 --- a/liteeth/core/mac/__init__.py +++ b/liteeth/core/mac/__init__.py @@ -16,10 +16,10 @@ class LiteEthMAC(Module, AutoCSR): self.submodules.packetizer = LiteEthMACPacketizer() self.submodules.depacketizer = LiteEthMACDepacketizer() self.comb += [ - Record.connect(self.crossbar.master.source, self.packetizer.sink), - Record.connect(self.packetizer.source, self.core.sink), - Record.connect(self.core.source, self.depacketizer.sink), - Record.connect(self.depacketizer.source, self.crossbar.master.sink) + self.crossbar.master.source.connect(self.packetizer.sink), + self.packetizer.source.connect(self.core.sink), + self.core.source.connect(self.depacketizer.sink), + self.depacketizer.source.connect(self.crossbar.master.sink) ] elif interface == "wishbone": self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2) diff --git a/liteeth/core/mac/core/crc.py b/liteeth/core/mac/core/crc.py index a36fefd..d51fc33 100644 --- a/liteeth/core/mac/core/crc.py +++ b/liteeth/core/mac/core/crc.py @@ -160,7 +160,7 @@ class LiteEthMACCRCInserter(Module): fsm.act("COPY", crc.ce.eq(sink.stb & source.ack), crc.data.eq(sink.data), - Record.connect(sink, source), + sink.connect(source, leave_out=set(["eop"])), source.eop.eq(0), If(sink.stb & sink.eop & source.ack, NextState("INSERT"), @@ -245,7 +245,7 @@ class LiteEthMACCRCChecker(Module): fifo_in.eq(sink.stb & (~fifo_full | fifo_out)), fifo_out.eq(source.stb & source.ack), - Record.connect(sink, fifo.sink), + sink.connect(fifo.sink, leave_out=set(["stb", "ack"])), fifo.sink.stb.eq(fifo_in), self.sink.ack.eq(fifo_in), diff --git a/liteeth/core/mac/core/gap.py b/liteeth/core/mac/core/gap.py index 8b5f516..464f162 100644 --- a/liteeth/core/mac/core/gap.py +++ b/liteeth/core/mac/core/gap.py @@ -21,7 +21,7 @@ class LiteEthMACGap(Module): self.submodules.fsm = fsm = FSM(reset_state="COPY") fsm.act("COPY", counter_reset.eq(1), - Record.connect(sink, source), + sink.connect(source), If(sink.stb & sink.eop & sink.ack, NextState("GAP") ) diff --git a/liteeth/core/mac/core/padding.py b/liteeth/core/mac/core/padding.py index d1f4885..9308bc6 100644 --- a/liteeth/core/mac/core/padding.py +++ b/liteeth/core/mac/core/padding.py @@ -27,7 +27,7 @@ class LiteEthMACPaddingInserter(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", - Record.connect(sink, source), + sink.connect(source), If(source.stb & source.ack, counter_ce.eq(1), If(sink.eop, @@ -59,5 +59,5 @@ class LiteEthMACPaddingChecker(Module): # XXX see if we should drop the packet when # payload size < minimum ethernet payload size - self.comb += Record.connect(sink, source) + self.comb += sink.connect(source) diff --git a/liteeth/core/mac/core/preamble.py b/liteeth/core/mac/core/preamble.py index 149e720..359d40a 100644 --- a/liteeth/core/mac/core/preamble.py +++ b/liteeth/core/mac/core/preamble.py @@ -49,7 +49,7 @@ class LiteEthMACPreambleInserter(Module): self.source.last_be.eq(self.sink.last_be) ] fsm.act("COPY", - Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])), + self.sink.connect(self.source, leave_out=set(["data", "last_be"])), self.source.sop.eq(0), If(self.sink.stb & self.sink.eop & self.source.ack, @@ -142,7 +142,7 @@ class LiteEthMACPreambleChecker(Module): self.source.last_be.eq(self.sink.last_be) ] fsm.act("COPY", - Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])), + self.sink.connect(self.source, leave_out=set(["data", "last_be"])), self.source.sop.eq(sop), clr_sop.eq(self.source.stb & self.source.ack), diff --git a/liteeth/core/mac/frontend/wishbone.py b/liteeth/core/mac/frontend/wishbone.py index 17016e0..b4fabf1 100644 --- a/liteeth/core/mac/frontend/wishbone.py +++ b/liteeth/core/mac/frontend/wishbone.py @@ -17,8 +17,8 @@ class LiteEthMACWishboneInterface(Module, AutoCSR): sram_depth = buffer_depth//(dw//8) self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots) self.comb += [ - Record.connect(self.sink, self.sram.sink), - Record.connect(self.sram.source, self.source) + self.sink.connect(self.sram.sink), + self.sram.source.connect(self.source) ] # Wishbone interface diff --git a/liteeth/core/udp.py b/liteeth/core/udp.py index 56d1cf2..d4cbe4f 100644 --- a/liteeth/core/udp.py +++ b/liteeth/core/udp.py @@ -39,15 +39,15 @@ class LiteEthUDPCrossbar(LiteEthCrossbar): eth_udp_user_description(8)) self.submodules += converter self.comb += [ - Record.connect(user_port.sink, converter.sink), - Record.connect(converter.source, internal_port.sink) + user_port.sink.connect(converter.sink), + converter.source.connect(internal_port.sink) ] converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw)) self.submodules += converter self.comb += [ - Record.connect(internal_port.source, converter.sink), - Record.connect(converter.source, user_port.source) + internal_port.source.connect(converter.sink), + converter.source.connect(user_port.source) ] self.users[udp_port] = internal_port else: @@ -93,7 +93,7 @@ class LiteEthUDPTX(Module): ) ) fsm.act("SEND", - Record.connect(packetizer.source, source), + packetizer.source.connect(source), source.length.eq(packetizer.sink.length), source.protocol.eq(udp_protocol), source.ip_address.eq(sink.ip_address), @@ -120,7 +120,7 @@ class LiteEthUDPRX(Module): # # # self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer() - self.comb += Record.connect(sink, depacketizer.sink) + self.comb += sink.connect(depacketizer.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -177,11 +177,11 @@ class LiteEthUDP(Module): self.submodules.rx = rx = LiteEthUDPRX(ip_address) ip_port = ip.crossbar.get_port(udp_protocol) self.comb += [ - Record.connect(tx.source, ip_port.sink), - Record.connect(ip_port.source, rx.sink) + tx.source.connect(ip_port.sink), + ip_port.source.connect(rx.sink) ] self.submodules.crossbar = crossbar = LiteEthUDPCrossbar() self.comb += [ - Record.connect(crossbar.master.source, tx.sink), - Record.connect(rx.source, crossbar.master.sink) + crossbar.master.source.connect(tx.sink), + rx.source.connect(crossbar.master.sink) ] diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index 9193a1f..f241103 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -46,7 +46,7 @@ class LiteEthEtherbonePacketTX(Module): ) ) fsm.act("SEND", - Record.connect(packetizer.source, source), + packetizer.source.connect(source), source.src_port.eq(udp_port), source.dst_port.eq(udp_port), source.ip_address.eq(sink.ip_address), @@ -73,7 +73,7 @@ class LiteEthEtherbonePacketRX(Module): # # # self.submodules.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer() - self.comb += Record.connect(sink, depacketizer.sink) + self.comb += sink.connect(depacketizer.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -133,8 +133,8 @@ class LiteEthEtherbonePacket(Module): self.submodules.rx = rx = LiteEthEtherbonePacketRX() udp_port = udp.crossbar.get_port(udp_port, dw=32) self.comb += [ - Record.connect(tx.source, udp_port.sink), - Record.connect(udp_port.source, rx.sink) + tx.source.connect(udp_port.sink), + udp_port.source.connect(rx.sink) ] self.sink, self.source = self.tx.sink, self.rx.source @@ -157,7 +157,7 @@ class LiteEthEtherboneProbe(Module): ) ) fsm.act("PROBE_RESPONSE", - Record.connect(sink, source), + sink.connect(source), source.pf.eq(0), source.pr.eq(1), If(source.stb & source.eop & source.ack, @@ -194,7 +194,7 @@ class LiteEthEtherboneRecordReceiver(Module): fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True) self.submodules += fifo - self.comb += Record.connect(sink, fifo.sink) + self.comb += sink.connect(fifo.sink) base_addr = Signal(32) base_addr_update = Signal() @@ -278,7 +278,7 @@ class LiteEthEtherboneRecordSender(Module): # TODO: optimize ressources (no need to store parameters as datas) pbuffer = Buffer(eth_etherbone_mmap_description(32), buffer_depth) self.submodules += pbuffer - self.comb += Record.connect(sink, pbuffer.sink) + self.comb += sink.connect(pbuffer.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -332,8 +332,8 @@ class LiteEthEtherboneRecord(Module): self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer() self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver() self.comb += [ - Record.connect(sink, depacketizer.sink), - Record.connect(depacketizer.source, receiver.sink) + sink.connect(depacketizer.sink), + depacketizer.source.connect(receiver.sink) ] if endianness is "big": self.comb += receiver.sink.data.eq(reverse_bytes(depacketizer.source.data)) @@ -350,8 +350,8 @@ class LiteEthEtherboneRecord(Module): self.submodules.sender = sender = LiteEthEtherboneRecordSender() self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer() self.comb += [ - Record.connect(sender.source, packetizer.sink), - Record.connect(packetizer.source, source), + sender.source.connect(packetizer.sink), + packetizer.source.connect(source), # XXX improve this source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header.length), source.ip_address.eq(last_ip_address) @@ -453,6 +453,6 @@ class LiteEthEtherbone(Module): # create mmap ŵishbone master self.submodules.master = master = LiteEthEtherboneWishboneMaster() self.comb += [ - Record.connect(record.receiver.source, master.sink), - Record.connect(master.source, record.sender.sink) + record.receiver.source.connect(master.sink), + master.source.connect(record.sender.sink) ] diff --git a/liteeth/frontend/tty.py b/liteeth/frontend/tty.py index 02ff844..75be202 100644 --- a/liteeth/frontend/tty.py +++ b/liteeth/frontend/tty.py @@ -19,7 +19,7 @@ class LiteEthTTYTX(Module): ] else: self.submodules.fifo = fifo = SyncFIFO([("data", 8)], fifo_depth) - self.comb += Record.connect(sink, fifo.sink) + self.comb += sink.connect(fifo.sink) level = Signal(max=fifo_depth) level_update = Signal() @@ -94,7 +94,7 @@ class LiteEthTTYRX(Module): fifo.sink.stb.eq(sink.stb & valid), fifo.sink.data.eq(sink.data), sink.ack.eq(fifo.sink.ack), - Record.connect(fifo.source, source) + fifo.source.connect(source) ] @@ -106,7 +106,7 @@ class LiteEthTTY(Module): self.submodules.rx = rx = LiteEthTTYRX(ip_address, udp_port, rx_fifo_depth) udp_port = udp.crossbar.get_port(udp_port, dw=8) self.comb += [ - Record.connect(tx.source, udp_port.sink), - Record.connect(udp_port.source, rx.sink) + tx.source.connect(udp_port.sink), + udp_port.source.connect(rx.sink) ] self.sink, self.source = self.tx.sink, self.rx.source diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index 7df12c8..25a5eab 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -38,9 +38,9 @@ class LiteEthPHYGMIIMIITX(Module): self.submodules += demux self.comb += [ demux.sel.eq(mode == modes["MII"]), - Record.connect(sink, demux.sink), - Record.connect(demux.source0, gmii_tx.sink), - Record.connect(demux.source1, mii_tx.sink), + sink.connect(demux.sink), + demux.source0.connect(gmii_tx.sink), + demux.source1.connect(mii_tx.sink), ] if hasattr(pads, "tx_er"): @@ -78,9 +78,9 @@ class LiteEthPHYGMIIMIIRX(Module): self.submodules += mux self.comb += [ mux.sel.eq(mode == modes["MII"]), - Record.connect(gmii_rx.source, mux.sink0), - Record.connect(mii_rx.source, mux.sink1), - Record.connect(mux.source, source) + gmii_rx.source.connect(mux.sink0), + mii_rx.source.connect(mux.sink1), + mux.source.connect(source) ] diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index ce49a8a..cdbeb1e 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -66,7 +66,7 @@ class LiteEthPHYMIIRX(Module): converter.sink.sop.eq(sop), converter.sink.eop.eq(~pads.dv) ] - self.comb += Record.connect(converter.source, source) + self.comb += converter.source.connect(source) class LiteEthPHYMIICRG(Module, AutoCSR): diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 71e32f3..fc38113 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -89,7 +89,7 @@ class LiteEthPHYRMIIRX(Module): NextState("IDLE") ) ) - self.comb += Record.connect(converter.source, source) + self.comb += converter.source.connect(source) class LiteEthPHYRMIICRG(Module, AutoCSR): diff --git a/test/mac_core_tb.py b/test/mac_core_tb.py index 9bfeb77..9acde2e 100644 --- a/test/mac_core_tb.py +++ b/test/mac_core_tb.py @@ -33,10 +33,10 @@ class TB(Module): ] self.comb += [ - Record.connect(self.streamer.source, self.streamer_randomizer.sink), - Record.connect(self.streamer_randomizer.source, self.core.sink), - Record.connect(self.core.source, self.logger_randomizer.sink), - Record.connect(self.logger_randomizer.source, self.logger.sink) + self.streamer.source.connect(self.streamer_randomizer.sink), + self.streamer_randomizer.source.connect(self.core.sink), + self.core.source.connect(self.logger_randomizer.sink), + self.logger_randomizer.source.connect(self.logger.sink) ] def gen_simulation(self, selfp): diff --git a/test/udp_tb.py b/test/udp_tb.py index 780a5d2..c71d963 100644 --- a/test/udp_tb.py +++ b/test/udp_tb.py @@ -27,12 +27,12 @@ class TB(Module): self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw)) self.submodules.logger = PacketLogger(eth_udp_user_description(dw)) self.comb += [ - Record.connect(self.streamer.source, udp_port.sink), + self.streamer.source.connect(udp_port.sink), udp_port.sink.ip_address.eq(0x12345678), udp_port.sink.src_port.eq(0x1234), udp_port.sink.dst_port.eq(0x5678), udp_port.sink.length.eq(64//(dw//8)), - Record.connect(udp_port.source, self.logger.sink) + udp_port.source.connect(self.logger.sink) ] # use sys_clk for each clock_domain