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examples/targets: udpate analyzer

This commit is contained in:
Florent Kermarrec 2019-11-23 15:47:42 +01:00
parent dc8ddf6895
commit d3b2f3d361
4 changed files with 8 additions and 32 deletions
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10
examples/targets/base.py
View File

@ -59,10 +59,6 @@ set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
class BaseSoCDevel(BaseSoC): class BaseSoCDevel(BaseSoC):
csr_map = {
"analyzer": 20
}
csr_map.update(BaseSoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
BaseSoC.__init__(self, platform) BaseSoC.__init__(self, platform)
@ -122,7 +118,8 @@ class BaseSoCDevel(BaseSoC):
self.core_udp_rx_fsm_state, self.core_udp_rx_fsm_state,
self.core_udp_tx_fsm_state self.core_udp_tx_fsm_state
] ]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def do_finalize(self): def do_finalize(self):
BaseSoC.do_finalize(self) BaseSoC.do_finalize(self)
@ -141,7 +138,4 @@ class BaseSoCDevel(BaseSoC):
self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state) self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state)
] ]
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
default_subtarget = BaseSoC default_subtarget = BaseSoC

10
examples/targets/etherbone.py
View File

@ -18,10 +18,6 @@ class EtherboneSoC(BaseSoC):
class EtherboneSoCDevel(EtherboneSoC): class EtherboneSoCDevel(EtherboneSoC):
csr_map = {
"analyzer": 20
}
csr_map.update(EtherboneSoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
EtherboneSoC.__init__(self, platform) EtherboneSoC.__init__(self, platform)
@ -61,9 +57,7 @@ class EtherboneSoCDevel(EtherboneSoC):
self.etherbone.wishbone.bus.bte, self.etherbone.wishbone.bus.bte,
self.etherbone.wishbone.bus.err self.etherbone.wishbone.bus.err
] ]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
default_subtarget = EtherboneSoC default_subtarget = EtherboneSoC

10
examples/targets/tty.py
View File

@ -18,10 +18,6 @@ class TTYSoC(BaseSoC):
class TTYSoCDevel(TTYSoC): class TTYSoCDevel(TTYSoC):
csr_map = {
"analyzer": 20
}
csr_map.update(TTYSoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
TTYSoC.__init__(self, platform) TTYSoC.__init__(self, platform)
@ -34,9 +30,7 @@ class TTYSoCDevel(TTYSoC):
self.tty.source.ready, self.tty.source.ready,
self.tty.source.data self.tty.source.data
] ]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
default_subtarget = TTYSoC default_subtarget = TTYSoC

10
examples/targets/udp.py
View File

@ -29,10 +29,6 @@ class UDPSoC(BaseSoC):
class UDPSoCDevel(UDPSoC): class UDPSoCDevel(UDPSoC):
csr_map = {
"analyzer": 20
}
csr_map.update(UDPSoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
UDPSoC.__init__(self, platform) UDPSoC.__init__(self, platform)
@ -57,9 +53,7 @@ class UDPSoCDevel(UDPSoC):
self.loopback_32.source.ready, self.loopback_32.source.ready,
self.loopback_32.source.data self.loopback_32.source.data
] ]
self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096) self.submodules.analyzer = LiteScopeAnalyzer(debug, 4096, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
default_subtarget = UDPSoC default_subtarget = UDPSoC