add manifest, uplift setup.py to pass twine checks

This commit is contained in:
Tim Paine 2023-04-11 14:05:08 -04:00
parent 97dccdb294
commit d66457d2b0
3 changed files with 45 additions and 2 deletions

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@ -13,8 +13,18 @@ jobs:
# Install Tools
- name: Install Tools
run: |
sudo apt-get install wget build-essential python3
pip3 install setuptools
sudo apt-get install wget build-essential
- name: Set up Python 3.9
uses: actions/setup-python@v4
with:
python-version: "3.9"
cache: "pip"
cache-dependency-path: "setup.py"
- name: Install Python dependencies
run: |
python3 -m pip install setuptools
# Install (n)Migen / LiteX / Cores
- name: Install LiteX

10
MANIFEST.in Normal file
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@ -0,0 +1,10 @@
graft liteeth
include CONTRIBUTORS
include LICENSE
graft doc
prune bench
prune examples
prune test

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@ -4,9 +4,16 @@ from setuptools import setup
from setuptools import find_packages
with open("README.md", "r") as fp:
long_description = fp.read()
setup(
name="liteeth",
version="2022.12",
description="Small footprint and configurable Ethernet core",
long_description=long_description,
long_description_content_type="text/markdown",
author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr",
@ -14,8 +21,24 @@ setup(
test_suite="test",
license="BSD",
python_requires="~=3.6",
install_requires=["pyyaml", "litex", "liteiclink"],
extras_require={
"develop": [
"setuptools"
]
},
packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
include_package_data=True,
keywords="HDL ASIC FPGA hardware design",
classifiers=[
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console",
"Development Status :: 3 - Alpha",
"Intended Audience :: Developers",
"License :: OSI Approved :: BSD License",
"Operating System :: OS Independent",
"Programming Language :: Python",
],
entry_points={
"console_scripts": [
"liteeth_gen=liteeth.gen:main",