From b9fb1f03ec8cf18680e6ca4e4bec332760600861 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 12 Feb 2020 14:36:11 +0100 Subject: [PATCH 1/4] Remove leftover classes in generator --- liteeth/gen.py | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index aaf425d..63a4a2d 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -161,18 +161,6 @@ _io = [ ), ] -# Platform ----------------------------------------------------------------------------------------- - -class LatticeCorePlatform(LatticePlatform): - name = "core" - def __init__(self, chip): - LatticePlatform.__init__(self, chip, _io) - -class XilinxCorePlatform(XilinxPlatform): - name = "core" - def __init__(self, chip): - XilinxPlatform.__init__(self, chip, _io) - # PHY Core ----------------------------------------------------------------------------------------- class PHYCore(SoCMini): From eea1086654eca090467d7625cea5a628eda59a2d Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 12 Feb 2020 14:39:34 +0100 Subject: [PATCH 2/4] Use builder arguments in generator --- liteeth/gen.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 63a4a2d..126e4a9 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -270,6 +270,8 @@ class UDPCore(PHYCore): def main(): parser = argparse.ArgumentParser(description="LiteEth standalone core generator") + builder_args(parser) + parser.set_defaults(output_dir="build") parser.add_argument("config", help="YAML config file") args = parser.parse_args() core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader) @@ -302,8 +304,14 @@ def main(): platform = platform) else: raise ValueError("Unknown core: {}".format(core_config["core"])) - builder = Builder(soc, output_dir="build", compile_gateware=False, csr_csv="build/csr.csv") + + builder_arguments = builder_argdict(args) + builder_arguments["compile_gateware"] = False + if builder_arguments["csr_csv"] is None: + builder_arguments["csr_csv"] = os.path.join(builder_arguments["output_dir"], "csr.csv") + + builder = Builder(soc, **builder_arguments) builder.build(build_name="liteeth_core") if __name__ == "__main__": - main() \ No newline at end of file + main() From ca9cbd15559aee15bb11e048e55d6e3dd4c3e846 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 12 Feb 2020 15:09:57 +0100 Subject: [PATCH 3/4] Move more options to config file --- examples/udp_s7phyrgmii.yml | 18 +++++++++--------- examples/wishbone_mii.yml | 15 +++++++-------- liteeth/gen.py | 24 +++++++++++------------- 3 files changed, 27 insertions(+), 30 deletions(-) diff --git a/examples/udp_s7phyrgmii.yml b/examples/udp_s7phyrgmii.yml index f3bd033..7b7c962 100644 --- a/examples/udp_s7phyrgmii.yml +++ b/examples/udp_s7phyrgmii.yml @@ -1,12 +1,12 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD -{ - # PHY ---------------------------------------------------------------------- - "phy": "LiteEthS7PHYRGMII", - "vendor": "xilinx", - # Core --------------------------------------------------------------------- - "core": "udp", - "mac_address": 0x10e2d5000000, - "ip_address": "192.168.1.50", -} +# PHY ---------------------------------------------------------------------- +phy: LiteEthS7PHYRGMII +vendor: xilinx +# Core --------------------------------------------------------------------- +clk_freq: 100e6 +core: udp +mac_address: 0x10e2d5000000 +ip_address: 192.168.1.50 +port: 6000 diff --git a/examples/wishbone_mii.yml b/examples/wishbone_mii.yml index c10b8e8..a423df5 100644 --- a/examples/wishbone_mii.yml +++ b/examples/wishbone_mii.yml @@ -1,11 +1,10 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD -{ - # PHY ---------------------------------------------------------------------- - "phy": "LiteEthPHYMII", - "vendor": "xilinx", - # Core --------------------------------------------------------------------- - "core": "wishbone", - "endianness": "big", -} +# PHY ---------------------------------------------------------------------- +phy: LiteEthPHYMII +vendor: xilinx +# Core --------------------------------------------------------------------- +clk_freq: 100e6 +core: wishbone +endianness: big diff --git a/liteeth/gen.py b/liteeth/gen.py index 126e4a9..00d45fd 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -203,10 +203,10 @@ class MACCore(PHYCore): "ethmac": 0x50000000 }) - def __init__(self, phy, clk_freq, platform, endianness): - PHYCore.__init__(self, phy, clk_freq, platform) + def __init__(self, platform, core_config): + PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=endianness) + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"]) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") @@ -225,11 +225,11 @@ class MACCore(PHYCore): # UDP Core ----------------------------------------------------------------------------------------- class UDPCore(PHYCore): - def __init__(self, phy, clk_freq, mac_address, ip_address, port, platform): - PHYCore.__init__(self, phy, clk_freq, platform) + def __init__(self, platform, core_config): + PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform) - self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq) - udp_port = self.core.udp.crossbar.get_port(port, 8) + self.submodules.core = LiteEthUDPIPCore(self.ethphy, core_config["mac_address"], convert_ip(core_config["ip_address"]), core_config["clk_freq"]) + udp_port = self.core.udp.crossbar.get_port(core_config["port"], 8) # XXX avoid manual connect udp_sink = self.platform.request("udp_sink") self.comb += [ @@ -284,6 +284,8 @@ def main(): core_config[k] = replaces[r] if k == "phy": core_config[k] = getattr(liteeth_phys, core_config[k]) + if k == "clk_freq": + core_config[k] = int(float(core_config[k])) # Generate core -------------------------------------------------------------------------------- if core_config["vendor"] == "lattice": @@ -295,13 +297,9 @@ def main(): platform.add_extension(_io) if core_config["core"] == "wishbone": - soc = MACCore(phy=core_config["phy"], clk_freq=int(100e6), platform=platform, endianness=core_config["endianness"]) + soc = MACCore(platform, core_config) elif core_config["core"] == "udp": - soc = UDPCore(phy=core_config["phy"], clk_freq=int(100e6), - mac_address = core_config["mac_address"], - ip_address = core_config["ip_address"], - port = 6000, - platform = platform) + soc = UDPCore(platform, core_config) else: raise ValueError("Unknown core: {}".format(core_config["core"])) From 7a44209f77c53c8bd36dc0cb39fcebafd3a7658a Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 12 Feb 2020 15:10:59 +0100 Subject: [PATCH 4/4] Make memory/CSR regions customizable in config Also remove interrupt mapping, since it's unused without a CPU anyway. --- examples/wishbone_mii.yml | 3 +++ liteeth/gen.py | 13 +++---------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/examples/wishbone_mii.yml b/examples/wishbone_mii.yml index a423df5..875ec8f 100644 --- a/examples/wishbone_mii.yml +++ b/examples/wishbone_mii.yml @@ -8,3 +8,6 @@ vendor: xilinx clk_freq: 100e6 core: wishbone endianness: big + +mem_map: + ethmac: 0x50000000 diff --git a/liteeth/gen.py b/liteeth/gen.py index 00d45fd..10e0721 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -193,17 +193,10 @@ class PHYCore(SoCMini): # MAC Core ----------------------------------------------------------------------------------------- class MACCore(PHYCore): - interrupt_map = SoCCore.interrupt_map - interrupt_map.update({ - "ethmac": 2, - }) - - mem_map = SoCCore.mem_map - mem_map.update({ - "ethmac": 0x50000000 - }) - def __init__(self, platform, core_config): + self.mem_map.update(core_config.get("mem_map", {})) + self.csr_map.update(core_config.get("csr_map", {})) + PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"])