simulations working with litex and vpi

test/arp_tb.py

@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core.mac import LiteEthMAC
 from liteeth.core.arp import LiteEthARP

test/common.py

@@ -1,9 +1,8 @@
 import random
-import copy
+from copy import deepcopy
 
-from litex.gen.fhdl.std import *
-from litex.gen.flow.actor import Sink, Source
-from litex.gen.genlib.record import *
+from litex.gen import *
+from litex.soc.interconnect.stream import Sink, Source
 
 from liteeth.common import *
 
@@ -49,8 +48,8 @@ def comp(p1, p2):
 
 
 def check(p1, p2):
-    p1 = copy.deepcopy(p1)
-    p2 = copy.deepcopy(p2)
+    p1 = deepcopy(p1)
+    p2 = deepcopy(p2)
     if isinstance(p1, int):
         return 0, 1, int(p1 != p2)
     else:
@@ -94,7 +93,7 @@ class PacketStreamer(Module):
         self.packet.done = True
 
     def send(self, packet):
-        packet = copy.deepcopy(packet)
+        packet = deepcopy(packet)
         self.packets.append(packet)
         return packet
 

test/etherbone_tb.py

@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.frontend.etherbone import LiteEthEtherbone

test/icmp_tb.py

@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthIPCore
 

test/ip_tb.py

@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthIPCore
 

test/mac_core_tb.py

@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core.mac.core import LiteEthMACCore
 

test/mac_wishbone_tb.py

@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core.mac import LiteEthMAC
 

test/udp_tb.py

@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore