From d84d610104265d9c83bf98ee6f69a8ba5e590f1c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 13 Nov 2015 15:11:57 +0100
Subject: [PATCH] simulations working with litex and vpi

---
 test/arp_tb.py          |  6 +++---
 test/common.py          | 13 ++++++-------
 test/etherbone_tb.py    |  6 +++---
 test/icmp_tb.py         |  6 +++---
 test/ip_tb.py           |  6 +++---
 test/mac_core_tb.py     |  6 +++---
 test/mac_wishbone_tb.py |  6 +++---
 test/udp_tb.py          |  6 +++---
 8 files changed, 27 insertions(+), 28 deletions(-)

diff --git a/test/arp_tb.py b/test/arp_tb.py
index be482a7..4ad8d5a 100644
--- a/test/arp_tb.py
+++ b/test/arp_tb.py
@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core.mac import LiteEthMAC
 from liteeth.core.arp import LiteEthARP
diff --git a/test/common.py b/test/common.py
index a2f2486..fe92a6e 100644
--- a/test/common.py
+++ b/test/common.py
@@ -1,9 +1,8 @@
 import random
-import copy
+from copy import deepcopy
 
-from litex.gen.fhdl.std import *
-from litex.gen.flow.actor import Sink, Source
-from litex.gen.genlib.record import *
+from litex.gen import *
+from litex.soc.interconnect.stream import Sink, Source
 
 from liteeth.common import *
 
@@ -49,8 +48,8 @@ def comp(p1, p2):
 
 
 def check(p1, p2):
-    p1 = copy.deepcopy(p1)
-    p2 = copy.deepcopy(p2)
+    p1 = deepcopy(p1)
+    p2 = deepcopy(p2)
     if isinstance(p1, int):
         return 0, 1, int(p1 != p2)
     else:
@@ -94,7 +93,7 @@ class PacketStreamer(Module):
         self.packet.done = True
 
     def send(self, packet):
-        packet = copy.deepcopy(packet)
+        packet = deepcopy(packet)
         self.packets.append(packet)
         return packet
 
diff --git a/test/etherbone_tb.py b/test/etherbone_tb.py
index 4f19f2a..add9f9a 100644
--- a/test/etherbone_tb.py
+++ b/test/etherbone_tb.py
@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.frontend.etherbone import LiteEthEtherbone
diff --git a/test/icmp_tb.py b/test/icmp_tb.py
index 8a2f0f8..63a14c3 100644
--- a/test/icmp_tb.py
+++ b/test/icmp_tb.py
@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthIPCore
 
diff --git a/test/ip_tb.py b/test/ip_tb.py
index b1c7fe3..f8f2a54 100644
--- a/test/ip_tb.py
+++ b/test/ip_tb.py
@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthIPCore
 
diff --git a/test/mac_core_tb.py b/test/mac_core_tb.py
index a684dcc..a9e7311 100644
--- a/test/mac_core_tb.py
+++ b/test/mac_core_tb.py
@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core.mac.core import LiteEthMACCore
 
diff --git a/test/mac_wishbone_tb.py b/test/mac_wishbone_tb.py
index 7c69fed..61bb59e 100644
--- a/test/mac_wishbone_tb.py
+++ b/test/mac_wishbone_tb.py
@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core.mac import LiteEthMAC
 
diff --git a/test/udp_tb.py b/test/udp_tb.py
index ffc95fa..27df513 100644
--- a/test/udp_tb.py
+++ b/test/udp_tb.py
@@ -1,8 +1,8 @@
-from litex.gen.fhdl.std import *
-from litex.gen.bus import wishbone
-from litex.gen.bus.transactions import *
+from litex.gen import *
 from litex.gen.sim.generic import run_simulation
 
+from litex.soc.interconnect import wishbone
+
 from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore