core/arp: Move ARP cache logic to LiteEthARPCache and define interfaces.
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@ -154,6 +154,47 @@ class LiteEthARPRX(LiteXModule):
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)
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)
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# ARP Cache ----------------------------------------------------------------------------------------
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class LiteEthARPCache(LiteXModule):
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def __init__(self, entries, clk_freq):
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assert entries == 1
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# Update interface.
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self.update = stream.Endpoint([("ip_address", 32), ("mac_address", 48)])
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# Request/Response interface.
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self.request = stream.Endpoint([("ip_address", 32)])
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self.response = stream.Endpoint([("mac_address", 48), ("error", 1)])
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# # #
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# Note: Store only 1 IP/MAC couple, can be improved with a real
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# table in the future to improve performance when packets are
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# targeting multiple destinations.
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cached_valid = Signal()
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cached_ip_address = Signal(32, reset_less=True)
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cached_mac_address = Signal(48, reset_less=True)
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self.cached_timer = WaitTimer(int(clk_freq*10))
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self.comb += self.update.ready.eq(1)
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self.sync += [
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If(self.update.valid,
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cached_valid.eq(1),
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cached_ip_address.eq(self.update.ip_address),
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cached_mac_address.eq(self.update.mac_address),
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).Else(
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If(self.cached_timer.done,
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cached_valid.eq(0)
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)
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)
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]
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self.comb += self.cached_timer.wait.eq(~self.update.valid)
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self.comb += self.request.ready.eq(1)
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self.comb += self.response.valid.eq(self.request.valid)
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self.comb += self.response.error.eq(~cached_valid | (self.request.ip_address != cached_ip_address))
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self.comb += self.response.mac_address.eq(cached_mac_address)
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# ARP Table ----------------------------------------------------------------------------------------
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class LiteEthARPTable(LiteXModule):
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@ -174,27 +215,7 @@ class LiteEthARPTable(LiteXModule):
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self.request_timer = WaitTimer(100e-3*clk_freq)
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self.comb += self.request_timer.wait.eq(request_pending & ~self.request_timer.done)
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# Note: Store only 1 IP/MAC couple, can be improved with a real
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# table in the future to improve performance when packets are
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# targeting multiple destinations.
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cached_update = Signal()
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cached_valid = Signal()
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cached_ip_address = Signal(32, reset_less=True)
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cached_mac_address = Signal(48, reset_less=True)
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cached_timer = WaitTimer(100e-3*clk_freq)
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self.submodules += cached_timer
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self.sync += [
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If(cached_update,
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cached_valid.eq(1),
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cached_ip_address.eq(sink.ip_address),
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cached_mac_address.eq(sink.mac_address),
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).Else(
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If(cached_timer.done,
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cached_valid.eq(0)
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)
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)
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]
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self.comb += cached_timer.wait.eq(~cached_update)
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self.cache = cache = LiteEthARPCache(entries=1, clk_freq=clk_freq)
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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@ -221,9 +242,13 @@ class LiteEthARPTable(LiteXModule):
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)
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fsm.act("UPDATE_TABLE",
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If(request_pending & (request_ip_address == sink.ip_address),
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cached_update.eq(1),
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NextValue(request_pending, 0),
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NextState("PRESENT_RESPONSE")
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cache.update.valid.eq(1),
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cache.update.ip_address.eq(sink.ip_address),
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cache.update.mac_address.eq(sink.mac_address),
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If(cache.update.ready,
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NextValue(request_pending, 0),
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NextState("PRESENT_RESPONSE")
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)
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).Else(
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NextState("IDLE")
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)
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@ -239,15 +264,18 @@ class LiteEthARPTable(LiteXModule):
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)
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)
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fsm.act("CHECK_TABLE",
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If(cached_valid & (request.ip_address == cached_ip_address),
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request.ready.eq(request.valid),
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NextState("PRESENT_RESPONSE"),
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).Else(
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cache.request.valid.eq(1),
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cache.request.ip_address.eq(request.ip_address),
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If(cache.response.valid,
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request.ready.eq(1),
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NextValue(request_counter, 0),
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NextValue(request_pending, 1),
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NextValue(request_ip_address, request.ip_address),
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NextState("SEND_REQUEST")
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If(cache.response.error,
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NextValue(request_counter, 0),
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NextValue(request_pending, 1),
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NextValue(request_ip_address, request.ip_address),
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NextState("SEND_REQUEST")
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).Else(
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NextState("PRESENT_RESPONSE"),
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)
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)
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)
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fsm.act("SEND_REQUEST",
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@ -261,7 +289,7 @@ class LiteEthARPTable(LiteXModule):
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)
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fsm.act("PRESENT_RESPONSE",
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response.valid.eq(1),
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response.mac_address.eq(cached_mac_address),
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response.mac_address.eq(cache.response.mac_address),
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If(response.ready,
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NextValue(response.failed, 0),
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NextState("IDLE")
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