diff --git a/README b/README
index fdb5611..baf3ae3 100644
--- a/README
+++ b/README
@@ -6,7 +6,7 @@
            Copyright 2012-2018 / EnjoyDigital
 
        A small footprint and configurable Ethernet core
-                powered by LiteX & Migen
+                powered by Migen & LiteX
 
 [> Intro
 --------
diff --git a/examples/make.py b/examples/make.py
index 0e68b0f..2447fbb 100755
--- a/examples/make.py
+++ b/examples/make.py
@@ -16,7 +16,7 @@ from migen.fhdl.structure import _Fragment
 from litex.build.tools import write_to_file
 from litex.build.xilinx.common import *
 
-from litex.soc.integration import cpu_interface
+from litex.soc.integration import export
 
 liteeth_path = "../"
 sys.path.append(liteeth_path) # XXX
@@ -94,8 +94,6 @@ if __name__ == "__main__":
     top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
     soc = top_class(platform, **top_kwargs)
     soc.finalize()
-    memory_regions = soc.get_memory_regions()
-    csr_regions = soc.get_csr_regions()
 
     # decode actions
     action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
@@ -116,7 +114,7 @@ if __name__ == "__main__":
       /____/_/\__/\__/___/\__/_//_/
 
   A small footprint and configurable Ethernet
-          core powered by Migen
+          core powered by Migen & LiteX
 ====== Building options: ======
 Platform:  {}
 Target:    {}
@@ -143,7 +141,7 @@ System Clk: {} MHz
         subprocess.call(["rm", "-rf", "build/*"])
 
     if actions["build-csr-csv"]:
-        csr_csv = cpu_interface.get_csr_csv(csr_regions)
+        csr_csv = export.get_csr_csv(soc.csr_regions)
         write_to_file(args.csr_csv, csr_csv)
 
     if actions["build-bitstream"]:
diff --git a/examples/targets/base.py b/examples/targets/base.py
index dc009ba..91ac5ef 100644
--- a/examples/targets/base.py
+++ b/examples/targets/base.py
@@ -31,8 +31,8 @@ class BaseSoC(SoCCore):
             ident="LiteEth Base Design",
             with_timer=False
         )
-        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
-        self.add_wb_master(self.cpu_or_bridge.wishbone)
+        self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
+        self.add_wb_master(self.bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
         # wishbone SRAM (to test Wishbone over UART and Etherbone)