diff --git a/examples/targets/base.py b/examples/targets/base.py
index 905c295..147273d 100644
--- a/examples/targets/base.py
+++ b/examples/targets/base.py
@@ -34,10 +34,6 @@ class BaseSoC(SoCCore):
         self.add_wb_master(serial_bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
-        # Wishbone SRAM (to test Wishbone over UART and Etherbone)
-        self.submodules.sram = wishbone.SRAM(1024)
-        self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
-
         # Ethernet PHY and UDP/IP stack
         self.submodules.ethphy  = ethphy = LiteEthPHY(
             clock_pads = platform.request("eth_clocks"),
diff --git a/examples/test/test_etherbone.py b/examples/test/test_etherbone.py
index 7bcffa0..1625044 100644
--- a/examples/test/test_etherbone.py
+++ b/examples/test/test_etherbone.py
@@ -5,7 +5,7 @@ import socket
 import time
 from litex.soc.tools.remote.etherbone import *
 
-SRAM_BASE = 0x02000000
+SRAM_BASE = 0x01000000
 
 socket = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)