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examples: use integrated sram instead of external one. (Also fix regression with new SoC that no longer support address decoders passed to add_wb_slave)

This commit is contained in:
Florent Kermarrec 2020-02-11 21:22:13 +01:00
parent 081bf46ca6
commit ddd0431373
2 changed files with 1 additions and 5 deletions
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4
examples/targets/base.py
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@ -34,10 +34,6 @@ class BaseSoC(SoCCore):
self.add_wb_master(serial_bridge.wishbone) self.add_wb_master(serial_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# Ethernet PHY and UDP/IP stack # Ethernet PHY and UDP/IP stack
self.submodules.ethphy = ethphy = LiteEthPHY( self.submodules.ethphy = ethphy = LiteEthPHY(
clock_pads = platform.request("eth_clocks"), clock_pads = platform.request("eth_clocks"),

2
examples/test/test_etherbone.py
View File

@ -5,7 +5,7 @@ import socket
import time import time
from litex.soc.tools.remote.etherbone import * from litex.soc.tools.remote.etherbone import *
SRAM_BASE = 0x02000000 SRAM_BASE = 0x01000000
socket = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) socket = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)