From dea35908c94873460643b48b162981590979e5e3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 23 Dec 2020 11:00:25 +0100 Subject: [PATCH] phy/rmii: add refclk_cd parameter (to select reference eth clock domain) and make clock_pads optional. --- liteeth/phy/rmii.py | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 679b8ce..e320c10 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -93,7 +93,7 @@ class LiteEthPHYRMIIRX(Module): class LiteEthPHYRMIICRG(Module, AutoCSR): - def __init__(self, clock_pads, pads, with_hw_init_reset): + def __init__(self, clock_pads, pads, refclk_cd, with_hw_init_reset): self._reset = CSRStorage() # # # @@ -101,11 +101,10 @@ class LiteEthPHYRMIICRG(Module, AutoCSR): # RX/TX clocks self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() - self.comb += [ - self.cd_eth_rx.clk.eq(ClockSignal("eth")), - self.cd_eth_tx.clk.eq(ClockSignal("eth")) - ] - self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx")) + self.comb += self.cd_eth_rx.clk.eq(ClockSignal(refclk_cd)) + self.comb += self.cd_eth_tx.clk.eq(ClockSignal(refclk_cd)) + if clock_pads is not None: + self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx")) # Reset self.reset = reset = Signal() @@ -126,8 +125,8 @@ class LiteEthPHYRMII(Module, AutoCSR): dw = 8 tx_clk_freq = 50e6 rx_clk_freq = 50e6 - def __init__(self, clock_pads, pads, with_hw_init_reset=True): - self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, with_hw_init_reset) + def __init__(self, clock_pads, pads, refclk_cd="eth", with_hw_init_reset=True): + self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, refclk_cd, with_hw_init_reset) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source