From e0f053e7a29a56a47840145bd245b9858e2dffa5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 10 Jul 2024 15:39:04 +0200 Subject: [PATCH] bench: Set margin to 0 on 1000/2500BaseX reference clock generation. --- bench/kc705.py | 2 +- bench/kcu105.py | 2 +- bench/xcu1525.py | 2 +- bench/xu8_st1.py | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/bench/kc705.py b/bench/kc705.py index 18755ee..8b535a2 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -37,7 +37,7 @@ class _CRG(LiteXModule): self.comb += main_pll.reset.eq(platform.request("cpu_reset")) main_pll.register_clkin(platform.request("clk200"), 200e6) main_pll.create_clkout(self.cd_sys, sys_clk_freq) - main_pll.create_clkout(self.cd_eth, 200e6) + main_pll.create_clkout(self.cd_eth, 200e6, margin=0) # Bench SoC ---------------------------------------------------------------------------------------- diff --git a/bench/kcu105.py b/bench/kcu105.py index d709853..e68c002 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -37,7 +37,7 @@ class _CRG(LiteXModule): self.comb += main_pll.reset.eq(platform.request("cpu_reset")) main_pll.register_clkin(platform.request("clk125"), 125e6) main_pll.create_clkout(self.cd_sys, sys_clk_freq) - main_pll.create_clkout(self.cd_eth, 200e6) + main_pll.create_clkout(self.cd_eth, 200e6, margin=0) # Bench SoC ---------------------------------------------------------------------------------------- diff --git a/bench/xcu1525.py b/bench/xcu1525.py index 5cf08d7..af04321 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -37,7 +37,7 @@ class _CRG(LiteXModule): self.main_pll = main_pll = USPMMCM(speedgrade=-2) main_pll.register_clkin(platform.request("clk300"), 300e6) main_pll.create_clkout(self.cd_sys, sys_clk_freq) - main_pll.create_clkout(self.cd_eth, 200e6) + main_pll.create_clkout(self.cd_eth, 200e6, margin=0) # Bench SoC ---------------------------------------------------------------------------------------- diff --git a/bench/xu8_st1.py b/bench/xu8_st1.py index 5f4ec93..ae4df6e 100755 --- a/bench/xu8_st1.py +++ b/bench/xu8_st1.py @@ -36,7 +36,7 @@ class _CRG(LiteXModule): self.pll = pll = USMMCM(speedgrade=-1) pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_eth, 200e6) + pll.create_clkout(self.cd_eth, 200e6, margin=0) # Bench SoC ----------------------------------------------------------------------------------------