Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

bench: Set margin to 0 on 1000/2500BaseX reference clock generation.

This commit is contained in:
Florent Kermarrec 2024-07-10 15:39:04 +02:00
parent 08c10774b5
commit e0f053e7a2
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bench/kc705.py
View File

@ -37,7 +37,7 @@ class _CRG(LiteXModule):
self.comb += main_pll.reset.eq(platform.request("cpu_reset")) self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk200"), 200e6) main_pll.register_clkin(platform.request("clk200"), 200e6)
main_pll.create_clkout(self.cd_sys, sys_clk_freq) main_pll.create_clkout(self.cd_sys, sys_clk_freq)
main_pll.create_clkout(self.cd_eth, 200e6) main_pll.create_clkout(self.cd_eth, 200e6, margin=0)
# Bench SoC ---------------------------------------------------------------------------------------- # Bench SoC ----------------------------------------------------------------------------------------

2
bench/kcu105.py
View File

@ -37,7 +37,7 @@ class _CRG(LiteXModule):
self.comb += main_pll.reset.eq(platform.request("cpu_reset")) self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk125"), 125e6) main_pll.register_clkin(platform.request("clk125"), 125e6)
main_pll.create_clkout(self.cd_sys, sys_clk_freq) main_pll.create_clkout(self.cd_sys, sys_clk_freq)
main_pll.create_clkout(self.cd_eth, 200e6) main_pll.create_clkout(self.cd_eth, 200e6, margin=0)
# Bench SoC ---------------------------------------------------------------------------------------- # Bench SoC ----------------------------------------------------------------------------------------

2
bench/xcu1525.py
View File

@ -37,7 +37,7 @@ class _CRG(LiteXModule):
self.main_pll = main_pll = USPMMCM(speedgrade=-2) self.main_pll = main_pll = USPMMCM(speedgrade=-2)
main_pll.register_clkin(platform.request("clk300"), 300e6) main_pll.register_clkin(platform.request("clk300"), 300e6)
main_pll.create_clkout(self.cd_sys, sys_clk_freq) main_pll.create_clkout(self.cd_sys, sys_clk_freq)
main_pll.create_clkout(self.cd_eth, 200e6) main_pll.create_clkout(self.cd_eth, 200e6, margin=0)
# Bench SoC ---------------------------------------------------------------------------------------- # Bench SoC ----------------------------------------------------------------------------------------

2
bench/xu8_st1.py
View File

@ -36,7 +36,7 @@ class _CRG(LiteXModule):
self.pll = pll = USMMCM(speedgrade=-1) self.pll = pll = USMMCM(speedgrade=-1)
pll.register_clkin(platform.request("clk100"), 100e6) pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_eth, 200e6) pll.create_clkout(self.cd_eth, 200e6, margin=0)
# Bench SoC ---------------------------------------------------------------------------------------- # Bench SoC ----------------------------------------------------------------------------------------