phy/gmii: enable use of gmii phy on non Xilinx devices

README

@@ -41,8 +41,8 @@ design flow by generating the verilog rtl that you will use as a standard core.
 - Hardware UDP/IP stack with ARP and ICMP
 - lwIP and uIP TCP/IP stacks ported and tested on lm32 and mor1kx
 
-[> Proven
-----------
+[> FPGA Proven
+---------------
 LiteEth is already used in commercial and open-source designs:
 - MiSoC: http://m-labs.hk/gateware.html
 - ARTIQ: http://m-labs.hk/artiq/index.html

liteeth/phy/gmii.py

@@ -60,12 +60,15 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
         # TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
         #      MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
         self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
-        # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
-        self.specials += Instance("BUFGMUX",
-                                  i_I0=self.cd_eth_rx.clk,
-                                  i_I1=clock_pads.tx,
-                                  i_S=mii_mode,
-                                  o_O=self.cd_eth_tx.clk)
+        if isinstance(mii_mode, int) and (mii_mode == 0):
+        	self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
+        else:
+        	# XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
+        	self.specials += Instance("BUFGMUX",
+            	                      i_I0=self.cd_eth_rx.clk,
+                	                  i_I1=clock_pads.tx,
+                    	              i_S=mii_mode,
+                        	          o_O=self.cd_eth_tx.clk)
 
         if with_hw_init_reset:
             reset = Signal()
@@ -88,11 +91,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 class LiteEthPHYGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
-                                                pads,
-                                                with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
-                                                "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
-                                                "eth_rx")
+        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
+        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx")
+        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx")
         self.sink, self.source = self.tx.sink, self.rx.source